Patents by Inventor Der-Tsyr Fan
Der-Tsyr Fan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7718488Abstract: Self-aligned split-gate flash memory cell array and process of fabrication in which erase and select gates are positioned on opposite sides of stacked floating and control gates, with source regions in the substrate beneath the erase gates, bit line diffusions which are partially overlapped by select gates at the ends of the rows of the cells. The floating and control gates are self-aligned with each other, and the erase and select gates are split from but self-aligned with the stacked gates. With the floating gates surrounded by the other gates and the source regions, high voltage coupling for both programming and erase operations is significantly enhanced. The memory cells are substantially smaller than prior art cells, and the array is biased so that all of the memory cells in it can be erased simultaneously, while programming is bit selectable.Type: GrantFiled: April 27, 2006Date of Patent: May 18, 2010Assignee: Silicon Storage Technology, Inc.Inventors: Chiou-Feng Chen, Prateep Tuntasood, Der-Tsyr Fan
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Patent number: 7668013Abstract: A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end. The flash memory cell has a plurality of stacked pairs of floating gates and control gates with the floating gates positioned over portions of the channel region and are insulated therefrom, and each control gate over a floating gate and insulated therefrom. The flash memory cell further has a plurality of erase gates over the channel region which are insulated therefrom, with an erase gate between each pair of stacked pair of floating gate and control gate. In a method of erasing the flash memory cell, a pulse of a first positive voltage is applied to alternating erase gates (“first alternating gates”).Type: GrantFiled: February 7, 2008Date of Patent: February 23, 2010Assignee: Silicon Storage Technology, Inc.Inventors: Geeng-Chuan Michael Chern, Ben Sheen, Jonathan Pabustan, Prateep Tuntasood, Der-Tsyr Fan, Yaw Wen Hu
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Patent number: 7646641Abstract: NAND flash memory cell array having control gates and charge storage gates stacked in pairs arranged in rows between a bit line diffusion and a common source diffusion, with select gates on both sides of each of the pairs of stacked gates. The gates in each stacked pair are self-aligned with each other, and the charge storage gates are either a nitride or a combination of nitride and oxide. Programming is done by hot electron injection from silicon substrate to the charge storage gates to build up a negative charge in the charge storage gates. Erasing is done by channel tunneling from the charge storage gates to the silicon substrate or by hot hole injection from the silicon substrate to the charge storage gates. The array is biased so that all of the memory cells can be erased simultaneously, while programming is bit selectable.Type: GrantFiled: June 15, 2004Date of Patent: January 12, 2010Assignee: Silicon Storage Technology, Inc.Inventors: Chiou-Feng Chen, Der-Tsyr Fan, Prateep Tuntasood
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Patent number: 7598561Abstract: Semiconductor memory array and process of fabrication in which a plurality of bit line diffusions are formed in a substrate, and memory cells formed in pairs between the bit line diffusions, with each of the pairs of cells having first and second conductors adjacent to the bit line diffusions, floating gates beside the first and second conductors, an erase gate between the floating gates, and a source line diffusion in the substrate beneath the erase gate, and at least one additional conductor capacitively coupled to the floating gates. In some disclosed embodiments, the conductors adjacent to the bit line diffusions are word lines, and the additional conductors consist of either a pair of coupling gates which are coupled to respective ones of the floating gates or a single coupling gate which is coupled to both of the floating gates.Type: GrantFiled: May 5, 2006Date of Patent: October 6, 2009Assignee: Silicon Storage Technolgy, Inc.Inventors: Bomy Chen, Prateep Tuntasood, Der-Tsyr Fan
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Publication number: 20090201744Abstract: A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end. The flash memory cell has a plurality of stacked pairs of floating gates and control gates with the floating gates positioned over portions of the channel region and are insulated therefrom, and each control gate over a floating gate and insulated therefrom. The flash memory cell further has a plurality of erase gates over the channel region which are insulated therefrom, with an erase gate between each pair of stacked pair of floating gate and control gate. In a method of erasing the flash memory cell, a pulse of a first positive voltage is applied to alternating erase gates (“first alternating gates”).Type: ApplicationFiled: February 7, 2008Publication date: August 13, 2009Inventors: Geeng-Chuan Michael Chern, Ben Sheen, Jonathan Pabustan, Prateep Tuntasood, Der-Tsyr Fan, Yaw Wen Hu
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Patent number: 7501321Abstract: NAND flash memory cell array and fabrication process in which cells having memory gates and charge storage layers are densely packed, with the memory gates in adjacent cells either overlapping or self-aligned with each other. The memory cells are arranged in rows between bit line diffusions and a common source diffusion, with the charge storage layers positioned beneath the memory gates in the cells. The memory gates are either polysilicon or polycide, and the charge storage gates are either a nitride or the combination of nitride and oxide. Programming is done either by hot electron injection from silicon substrate to the charge storage gates to build up a negative charge in the charge storage gates or by hot hole injection from the silicon substrate to the charge storage gates to build up a positive charge in the charge storage gates. Erasure is done by channel tunneling from the charge storage gates to the silicon substrate or vice versa, depending on the programming method.Type: GrantFiled: September 27, 2006Date of Patent: March 10, 2009Assignee: Silicon Storage Technology, Inc.Inventors: Prateep Tuntasood, Der-Tsyr Fan, Chiou-Feng Chen
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Publication number: 20070257299Abstract: Semiconductor memory array and process of fabrication in which a plurality of bit line diffusions are formed in a substrate, and memory cells formed in pairs between the bit line diffusions, with each of the pairs of cells having first and second conductors adjacent to the bit line diffusions, floating gates beside the first and second conductors, an erase gate between the floating gates, and a source line diffusion in the substrate beneath the erase gate, and at least one additional conductor capacitively coupled to the floating gates. In some disclosed embodiments, the conductors adjacent to the bit line diffusions are word lines, and the additional conductors consist of either a pair of coupling gates which are coupled to respective ones of the floating gates or a single coupling gate which is coupled to both of the floating gates.Type: ApplicationFiled: May 5, 2006Publication date: November 8, 2007Applicant: Silicon Storage Technology, Inc.Inventors: Bomy Chen, Prateep Tuntasood, Der-Tsyr Fan
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Patent number: 7217621Abstract: Self-aligned split-gate NAND flash memory cell array and process of fabrication in which rows of self-aligned split-gate cells are formed between a bit line diffusion and a common source diffusion in the active area of a substrate. Each cell has control and floating gates which are stacked and self-aligned with each other, and erase and select gates which are split from and self-aligned with the stacked gates, with select gates at both ends of each row which partially overlap the bit line the source diffusions. The channel regions beneath the erase gates are heavily doped to reduce the resistance of the channel between the bit line and source diffusions, and the floating gates are surrounded by the other gates in a manner which provides significantly enhanced high voltage coupling to the floating gates from the other gates.Type: GrantFiled: November 16, 2005Date of Patent: May 15, 2007Assignee: Silicon Storage Technology, IncInventors: Chiou-Feng Chen, Caleb Yu-Sheng Cho, Ming-Jer Chen, Der-Tsyr Fan, Prateep Tuntasood
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Publication number: 20070032018Abstract: NAND flash memory cell array and fabrication process in which cells having memory gates and charge storage layers are densely packed, with the memory gates in adjacent cells either overlapping or self-aligned with each other. The memory cells are arranged in rows between bit line diffusions and a common source diffusion, with the charge storage layers positioned beneath the memory gates in the cells. The memory gates are either polysilicon or polycide, and the charge storage gates are either a nitride or the combination of nitride and oxide. Programming is done either by hot electron injection from silicon substrate to the charge storage gates to build up a negative charge in the charge storage gates or by hot hole injection from the silicon substrate to the charge storage gates to build up a positive charge in the charge storage gates. Erasure is done by channel tunneling from the charge storage gates to the silicon substrate or vice versa, depending on the programming method.Type: ApplicationFiled: September 27, 2006Publication date: February 8, 2007Applicant: SILICON STORAGE TECHNOLOGY, INC.Inventors: Prateep Tuntasood, Der-Tsyr Fan, Chiou-Feng Chen
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Publication number: 20060203552Abstract: Self-aligned split-gate flash memory cell array and process of fabrication in which erase and select gates are positioned on opposite sides of stacked floating and control gates, with source regions in the substrate beneath the erase gates, bit line diffusions which are partially overlapped by select gates at the ends of the rows of the cells. The floating and control gates are self-aligned with each other, and the erase and select gates are split from but self-aligned with the stacked gates. With the floating gates surrounded by the other gates and the source regions, high voltage coupling for both programming and erase operations is significantly enhanced. The memory cells are substantially smaller than prior art cells, and the array is biased so that all of the memory cells in it can be erased simultaneously, while programming is bit selectable.Type: ApplicationFiled: April 27, 2006Publication date: September 14, 2006Applicant: Actrans System Incorporation, USAInventors: Chiou-Feng Chen, Prateep Tuntasood, Der-Tsyr Fan
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Patent number: 7046552Abstract: Self-aligned split-gate flash memory cell array and process of fabrication in which erase and select gates are positioned on opposite sides of stacked floating and control gates, with source regions in the substrate beneath the erase gates, bit line diffusions which are partially overlapped by select gates at the ends of the rows of the cells. The floating and control gates are self-aligned with each other, and the erase and select gates are split from but self-aligned with the stacked gates. With the floating gates surrounded by the other gates and the source regions, high voltage coupling for both programming and erase operations is significantly enhanced. The memory cells are substantially smaller than prior art cells, and the array is biased so that all of the memory cells in it can be erased simultaneously, while programming is bit selectable.Type: GrantFiled: March 17, 2004Date of Patent: May 16, 2006Assignee: Actrans System Incorporation, USAInventors: Chiou-Feng Chen, Prateep Tuntasood, Der-Tsyr Fan
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Patent number: 7037787Abstract: Flash memory and process of fabrication in which memory cells are formed with select gates in trenches between stacked, self-aligned floating and control gates, with buried source and drain regions which are gated by the select gates. Erase paths are formed between projecting rounded edges of the floating gates and the select gates, and programming paths extend from the mid-channel regions between the select gates and floating gates through the gate oxide to the edges of the floating gates. Trenched select gates can be provided on one or both sides of the floating and control gates, depending upon array architecture, and the stacked gates and dielectric covering them are used as a self-aligned mask in etching the substrate and other materials to form the trenches.Type: GrantFiled: February 16, 2005Date of Patent: May 2, 2006Assignees: Actrans System Inc., Actrans System Incorporation, USAInventors: Der-Tsyr Fan, Jung-Chang Lu, Chiou-Feng Chen, Prateep Tuntasood
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Publication number: 20060068529Abstract: Self-aligned split-gate NAND flash memory cell array and process of fabrication in which rows of self-aligned split-gate cells are formed between a bit line diffusion and a common source diffusion in the active area of a substrate. Each cell has control and floating gates which are stacked and self-aligned with each other, and erase and select gates which are split from and self-aligned with the stacked gates, with select gates at both ends of each row which partially overlap the bit line the source diffusions. The channel regions beneath the erase gates are heavily doped to reduce the resistance of the channel between the bit line and source diffusions, and the floating gates are surrounded by the other gates in a manner which provides significantly enhanced high voltage coupling to the floating gates from the other gates.Type: ApplicationFiled: November 16, 2005Publication date: March 30, 2006Inventors: Chiou-Feng Chen, Caleb Yu-Sheng Cho, Ming-Jer Chen, Der-Tsyr Fan, Prateep Tuntasood
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Patent number: 6992929Abstract: Self-aligned split-gate NAND flash memory cell array and process of fabrication in which rows of self-aligned split-gate cells are formed between a bit line diffusion and a common source diffusion in the active area of a substrate. Each cell has control and floating gates which are stacked and self-aligned with each other, and erase and select gates which are split from and self-aligned with the stacked gates, with select gates at both ends of each row which partially overlap the bit line the source diffusions. The channel regions beneath the erase gates are heavily doped to reduce the resistance of the channel between the bit line and source diffusions, and the floating gates are surrounded by the other gates in a manner which provides significantly enhanced high voltage coupling to the floating gates from the other gates.Type: GrantFiled: March 17, 2004Date of Patent: January 31, 2006Assignee: Actrans System Incorporation, USAInventors: Chiou-Feng Chen, Caleb Yu-Sheng Cho, Ming-Jer Chen, Der-Tsyr Fan, Prateep Tuntasood
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Publication number: 20060017085Abstract: NAND flash memory cell array and fabrication process in which cells having memory gates and charge storage layers are densely packed, with the memory gates in adjacent cells either overlapping or self-aligned with each other. The memory cells are arranged in rows between bit line diffusions and a common source diffusion, with the charge storage layers positioned beneath the memory gates in the cells. The memory gates are either polysilicon or polycide, and the charge storage gates are either a nitride or the combination of nitride and oxide. Programming is done either by hot electron injection from silicon substrate to the charge storage gates to build up a negative charge in the charge storage gates or by hot hole injection from the silicon substrate to the charge storage gates to build up a positive charge in the charge storage gates. Erasure is done by channel tunneling from the charge storage gates to the silicon substrate or vice versa, depending on the programming method.Type: ApplicationFiled: July 26, 2004Publication date: January 26, 2006Inventors: Prateep Tuntasood, Der-Tsyr Fan, Chiou-Feng Chen
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Publication number: 20050276106Abstract: NAND flash memory cell array having control gates and charge storage gates stacked in pairs arranged in rows between a bit line diffusion and a common source diffusion, with select gates on both sides of each of the pairs of stacked gates. The gates in each stacked pair are self-aligned with each other, and the charge storage gates are either a nitride or a combination of nitride and oxide. Programming is done by hot electron injection from silicon substrate to the charge storage gates to build up a negative charge in the charge storage gates. Erasing is done by channel tunneling from the charge storage gates to the silicon substrate or by hot hole injection from the silicon substrate to the charge storage gates. The array is biased so that all of the memory cells can be erased simultaneously, while programming is bit selectable.Type: ApplicationFiled: June 15, 2004Publication date: December 15, 2005Inventors: Chiou-Feng Chen, Der-Tsyr Fan, Prateep Tuntasood
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Publication number: 20050207199Abstract: Self-aligned split-gate flash memory cell array and process of fabrication in which erase and select gates are positioned on opposite sides of stacked floating and control gates, with source regions in the substrate beneath the erase gates, bit line diffusions which are partially overlapped by select gates at the ends of the rows of the cells. The floating and control gates are self-aligned with each other, and the erase and select gates are split from but self-aligned with the stacked gates. With the floating gates surrounded by the other gates and the source regions, high voltage coupling for both programming and erase operations is significantly enhanced. The memory cells are substantially smaller than prior art cells, and the array is biased so that all of the memory cells in it can be erased simultaneously, while programming is bit selectable.Type: ApplicationFiled: March 17, 2004Publication date: September 22, 2005Inventors: Chiou-Feng Chen, Prateep Tuntasood, Der-Tsyr Fan
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Publication number: 20050207225Abstract: Self-aligned split-gate NAND flash memory cell array and process of fabrication in which rows of self-aligned split-gate cells are formed between a bit line diffusion and a common source diffusion in the active area of a substrate. Each cell has control and floating gates which are stacked and self-aligned with each other, and erase and select gates which are split from and self-aligned with the stacked gates, with select gates at both ends of each row which partially overlap the bit line the source diffusions. The channel regions beneath the erase gates are heavily doped to reduce the resistance of the channel between the bit line and source diffusions, and the floating gates are surrounded by the other gates in a manner which provides significantly enhanced high voltage coupling to the floating gates from the other gates.Type: ApplicationFiled: March 17, 2004Publication date: September 22, 2005Inventors: Chiou-Feng Chen, Caleb Cho, Ming-Jer Chen, Der-Tsyr Fan, Prateep Tuntasood
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Publication number: 20050145923Abstract: NAND flash memory cell array and fabrication process in which control gates and floating gates are stacked in pairs arranged in rows between a bit line diffusion and a common source diffusion, with select gates on both sides of each of the pairs of stacked gates.Type: ApplicationFiled: January 6, 2004Publication date: July 7, 2005Inventors: Chiou-Feng Chen, Prateep Tuntasood, Der-Tsyr Fan
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Publication number: 20050146937Abstract: Flash memory and process of fabrication in which memory cells are formed with select gates in trenches between stacked, self-aligned floating and control gates, with buried source and drain regions which are gated by the select gates. Erase paths are formed between projecting rounded edges of the floating gates and the select gates, and programming paths extend from the mid-channel regions between the select gates and floating gates through the gate oxide to the edges of the floating gates. Trenched select gates can be provided on one or both sides of the floating and control gates, depending upon array architecture, and the stacked gates and dielectric covering them are used as a self-aligned mask in etching the substrate and other materials to form the trenches.Type: ApplicationFiled: February 16, 2005Publication date: July 7, 2005Inventors: Der-Tsyr Fan, Jung-Chang Lu, Chiou-Feng Chen, Prateep Tuntasood