Patents by Inventor Der-Tsyr Fan
Der-Tsyr Fan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6894339Abstract: Flash memory and process of fabrication in which memory cells are formed with select gates in trenches between stacked, self-aligned floating and control gates, with buried source and drain regions which are gated by the select gates. Erase paths are formed between projecting rounded edges of the floating gates and the select gates, and programming paths extend from the mid-channel regions between the select gates and floating gates through the gate oxide to the edges of the floating gates. Trenched select gates can be provided on one or both sides of the floating and control gates, depending upon array architecture, and the stacked gates and dielectric covering them are used as a self-aligned mask in etching the substrate and other materials to form the trenches.Type: GrantFiled: January 2, 2003Date of Patent: May 17, 2005Assignees: Actrans System Inc., Actrans System Incorporation, USAInventors: Der-Tsyr Fan, Jung-Chang Lu, Chiou-Feng Chen, Prateep Tuntasood
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Patent number: 6885586Abstract: Self-aligned split-gate NAND flash memory cell array and method of fabrication in which a series of self-aligned split cells are formed between a bit line diffusion and a common source diffusion. Each cell has control and floating gates which are stacked and self-aligned with each other, and a third gate which is split from but self-aligned with the other two. In some disclosed embodiments, the split gates are utilized as erase gates, and in others they are utilized as select gates. The memory cells are substantially smaller than prior art cells, and the array is biased so that all of the memory cells in it can be erased simultaneously, while programming is bit selectable.Type: GrantFiled: September 19, 2002Date of Patent: April 26, 2005Assignee: Actrans System Inc.Inventors: Chiou-Feng Chen, Der-Tsyr Fan, Jung-Chang Lu, Prateep Tuntasood
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Publication number: 20040130947Abstract: Flash memory and process of fabrication in which memory cells are formed with select gates in trenches between stacked, self-aligned floating and control gates, with buried source and drain regions which are gated by the select gates. Erase paths are formed between projecting rounded edges of the floating gates and the select gates, and programming paths extend from the mid-channel regions between the select gates and floating gates through the gate oxide to the edges of the floating gates. Trenched select gates can be provided on one or both sides of the floating and control gates, depending upon array architecture, and the stacked gates and dielectric covering them are used as a self-aligned mask in etching the substrate and other materials to form the trenches.Type: ApplicationFiled: January 2, 2003Publication date: July 8, 2004Inventors: Der-Tsyr Fan, Jung-Chang Lu, Chiou-Feng Chen, Prateep Tuntasood
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Patent number: 6747310Abstract: Flash memory and process of fabrication in which vertically stacked pairs of floating gates and control gates are formed on opposite sides of a source diffusion in a substrate, an erase gate is formed directly above the source diffusion and between the stacked gates, select gates are formed on the sides of the stacked gates opposite the erase gate, programming paths extend from mid-channel regions in the substrate between the select gates and the stacked gates to the edge portions of the floating gates which face the select gates, and erase paths extend from the edge portions of the floating gates which face the erase gates to the source diffusion and to the erase gate. In some embodiments, the source regions are connected electrically to the erase gates, and in others the floating gates project laterally beyond the control gates on one or both sides of the control gates.Type: GrantFiled: October 7, 2002Date of Patent: June 8, 2004Assignee: Actrans System Inc.Inventors: Der-Tsyr Fan, Chiou-Feng Chen, Prateep Tuntasood
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Publication number: 20040065917Abstract: Flash memory and process of fabrication in which vertically stacked pairs of floating gates and control gates are formed on opposite sides of a source diffusion in a substrate, an erase gate is formed directly above the source diffusion and between the stacked gates, select gates are formed on the sides of the stacked gates opposite the erase gate, programming paths extend from mid-channel regions in the substrate between the select gates and the stacked gates to the edge portions of the floating gates which face the select gates, and erase paths extend from the edge portions of the floating gates which face the erase gates to the source diffusion and to the erase gate. In some embodiments, the source regions are connected electrically to the erase gates, and in others the floating gates project laterally beyond the control gates on one or both sides of the control gates.Type: ApplicationFiled: October 7, 2002Publication date: April 8, 2004Inventors: Der-Tsyr Fan, Chiou-Feng Chen, Prateep Tuntasood
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Publication number: 20040057286Abstract: Self-aligned split-gate NAND flash memory cell array and method of fabrication in which a series of self-aligned split cells are formed between a bit line diffusion and a common source diffusion. Each cell has control and floating gates which are stacked and self-aligned with each other, and a third gate which is split from but self-aligned with the other two. In some disclosed embodiments, the split gates are utilized as erase gates, and in others they are utilized as select gates. The memory cells are substantially smaller than prior art cells, and the array is biased so that all of the memory cells in it can be erased simultaneously, while programming is bit selectable.Type: ApplicationFiled: September 19, 2002Publication date: March 25, 2004Inventors: Chiou-Feng Chen, Der-Tsyr Fan, Jung-Chang Lu, Prateep Tuntasood
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Patent number: 6654291Abstract: Embodiments of the present invention are directed to an improved EEPROM (electrically erasable programmable read-only memory) in which the memory cells can be selectively erased. The EEPROM comprises a first memory cell having a first control gate and a first source, and a second memory cell having second control gate and a second source. If the first and second control gates are configured to receive a control gate voltage, the first source is configured to receive a first source voltage, and the second source is configured to receive a second source voltage different from the first source voltage so as to erase one of the first and second memory cells and to preserve another of the first and second memory cells.Type: GrantFiled: May 24, 2002Date of Patent: November 25, 2003Assignee: Mosel Vitelic, Inc.Inventors: Shang Tarng Jan, Der-Tsyr Fan
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Publication number: 20030002346Abstract: Embodiments of the present invention are directed to an improved EEPROM (electrically erasable programmable read-only memory) in which the memory cells can be selectively erased. The EEPROM comprises a first memory cell having a first control gate and a first source, and a second memory cell having second control gate and a second source. If the first and second control gates are configured to receive a control gate voltage, the first source is configured to receive a first source voltage, and the second source is configured to receive a second source voltage different from the first source voltage so as to erase one of the first and second memory cells and to preserve another of the first and second memory cells.Type: ApplicationFiled: May 24, 2002Publication date: January 2, 2003Applicant: MOSEL VITELIC, INC.Inventors: Shang Tarng Jan, Der-Tsyr Fan
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Patent number: 6380072Abstract: A method for manufacturing a semiconductor device having an excellent metallization is provided. The method includes the steps of a).Type: GrantFiled: November 29, 2000Date of Patent: April 30, 2002Assignee: Mosel Vitelic Inc.Inventors: John Chu, Der-Tsyr Fan, Chon-Shin Jou, Ting S. Wang
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Patent number: 6365064Abstract: The present invention provides a method for evenly immersing a wafer in a solution held in a solution chamber, which comprises the following steps: (1) placing at least one disk-shaped wafer inside a wafer holder which is used for vertically holding at least one wafer, (2) immersing the wafer holder into the solution vertically so that each wafer in the wafer holder can be vertically immersed into and react with the solution, (3) vertically rotating the wafer holder in the solution so as to invert each wafer in the wafer holder upside down, and (4) removing the wafer holder from the solution vertically after immersing the wafer in the solution for a predetermined period of time.Type: GrantFiled: November 23, 1998Date of Patent: April 2, 2002Assignee: Mosel Vitelic Inc.Inventors: Chung-Shih Tsai, Chou-Shin Jou, Der-Tsyr Fan
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Patent number: 6245608Abstract: A method of contact ion implantation is disclosed. Only one mask and a dosage-enhanced implantation is utilized to form different types of doped contact regions. A blanket ion implantation is first carried out, and all the contact regions of first and second type are formed with the first conductive type impurities. Then a mask is defined to cover the first type contact regions and expose the second type regions. A second ion implantation is now carried out to implant impurity ions of second conductive type into the second type contact regions. The dosage of these second conductive type ions is determined so that, the second type contact regions are convert from the first conductive type into section conductive type.Type: GrantFiled: June 14, 1999Date of Patent: June 12, 2001Assignee: Mosel Vitelic Inc.Inventors: Tsai-Sen Lin, Chon-Shin Jou, Der-Tsyr Fan
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Publication number: 20010000496Abstract: A method for manufacturing a semiconductor device having an excellent metallization is provided. The method includes the steps of a) providing a semiconductor substrate, b) forming a conductive layer on the semiconductor substrate, c) forming a dielectric layer on the conductive layer, d) forming a titanium nitride layer directly on the dielectric layer without contacting the conductive layer, and e) patternizing the titanium nitride layer, the dielectric layer and the conductive layer, wherein the dielectric layer is used for avoiding spontaneous electrochemical reaction between the titanium nitride layer and the conductive layer.Type: ApplicationFiled: November 29, 2000Publication date: April 26, 2001Applicant: Mosel Vitelic Inc.Inventors: John Chu, Der-Tsyr Fan, Chon-Shin Jou, Ting S. Wang
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Patent number: 6110801Abstract: A method of fabricating trench isolation is disclosed: firstly, the areas of trench isolation are formed on a silicon substrate, and then filled by depositing an oxide layer. Secondly, a process of planarization is performed to remove the extra oxide. After that, a layer of photo resist is coated and patterned, such that the areas of trench isolation are protected by the layer of photo resist. The oxide protected by the photo resist is not removed by the subsequent etching process. During the process of stripping the photo resist, the oxide at the edges of the areas of trench isolation will be also rounded and no more in the shape of right angle. Therefore, the kink effect in the prior arts is no more existent. Thereafter, a gate oxide layer and a polysilicon layer are formed in sequence. The trench isolation according to the present invention is thus accomplished.Type: GrantFiled: November 13, 1998Date of Patent: August 29, 2000Assignee: Mosel Vitelic Inc.Inventors: Chung-Shih Tsai, Der-Tsyr Fan
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Patent number: 5926715Abstract: A method of forming a LDD fabrication by automatic phosphoric silicate glass (PSG) doping is disclosed herein. A phosphoric silicate glass serves as a diffusion source. The phosphorous ions of phosphoric silicate glass can be driven into a substrate to form a lightly-doped drain (LDD)by a high temperature during a thermal annealing process. The diffusion method can prevent from the damage in the substrate and the increasing of leakage current. Additionally, a thermal oxide layer is formed on the gate electrode and the surface of the substrate by the thermal oxidation process. The thermal oxide layer can prevent ions from sequentially diffusing into the substrate during the subsequent thermal treatment process. Therefore, the present invention can effectively control the impurity concentration of the lightly-doped drain (LDD) to prevent from the impurity concentration of the LDD over high.Type: GrantFiled: June 4, 1997Date of Patent: July 20, 1999Assignee: Mosel Vitelic Inc.Inventors: Der-Tsyr Fan, Liang-Choo Hsia, Jr-Min Tsaur
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Patent number: 5882984Abstract: The present invention is a method for increasing the refresh time of DRAM. This invention is for decreasing the stress between the bird's beak of field oxide and silicon substrate by using fluorine ion implant before field oxidation and the optimal structure of LOCOS to effectively preventing the current leakage from the bird's beak of field oxide. Therefore, this invention can increase the refresh time of DRAM and greatly enhance the performance in DRAM.Type: GrantFiled: October 9, 1996Date of Patent: March 16, 1999Assignee: Mosel Vitelic Inc.Inventors: Der-Tsyr Fan, Chon-Shin Jou, Ting S. Wang
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Patent number: 5837578Abstract: A trenched stack-capacitor applied in a memory unit is formed through a simple process of manufacturing a stack capacitor with high density.Type: GrantFiled: July 16, 1997Date of Patent: November 17, 1998Assignee: Mosel Vitelic Inc.Inventors: Der-Tsyr Fan, Jyh-Min Tsaur, Chon-Shin Jou, Tings Wang
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Patent number: 5747378Abstract: A method of damage-free doping for forming a dynamic random access memory cell is disclosed herein. A phosphoric silicate glass is deposited as a diffusion source. The phosphorous ions of phosphoric silicate glass can be diffused into a substrate to form the source/drain regions by a high temperature during a thermal annealing process. Next, a thermal oxide layer is formed on the gate electrode and the surface of the substrate by the thermal oxidation process. The thermal oxide layer can prevent ions from diffusing into the substrate during the subsequent thermal treatment process. Therefore, the present invention can reduce the damage of a dynamic random access memory.Type: GrantFiled: May 27, 1997Date of Patent: May 5, 1998Assignee: Mosel Vitelic Inc.Inventors: Der-Tsyr Fan, Chon-Shin Jou, Ting-S. Wang