Abstract: A processor communication register (PCR) contained in each processor within a multiprocessor cluster network provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR within the cluster network and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs via a private protocol or dedicated wireless network, instantly allowing all of the other processors within the cluster network to see the change within the PCR data, and bypassing the cache subsystem.

Abstract: A method, system, and processor chip design for reducing the latency between completing a LARX operation and receiving the associated STCX operation to complete the update to the cache line. Each entry of the store queue of the issuing processor is provided an additional tracking bit (priority bit). The priority bit is set whenever a STCX operation is placed within the entry. During selection of an entry for dispatch by the arbitration logic, the arbitration logic scans the value of the priority bits of each eligible entry. An entry with the priority bit set is given priority in the selection process within architectural rules. That entry is then selected for dispatch as early as is possible within the established rules.

Abstract: A processor communication register (PCR) contained within a multiprocessor cluster system provides enhanced processor communication. The PCR stores information that is useful in pipelined or parallel multi-processing. Each processor cluster has exclusive rights to store to a sector within the PCR and has continuous access to read its contents. Each processor cluster updates its exclusive sector within the PCR, instantly allowing all of the other processors within the cluster network to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the processor cluster network by providing processor communications to be immediately networked and transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.

Abstract: A method and processor system that substantially eliminates data bus operations when completing updates of an entire cache line with a full store queue entry. The store queue within a processor chip is designed with a series of AND gates connecting individual bits of the byte enable bits of a corresponding entry. The AND output is fed to the STQ controller and signals when the entry is full. When full entries are selected for dispatch to the RC machines, the RC machine is signaled that the entry updates the entire cache line. The RC machine obtains write permission to the line, and then the RC machine overwrites the entire cache line. Because the entire cache line is overwritten, the data of the cache line is not retrieved when the request for the cache line misses at the cache or when data goes state before write permission is obtained by the RC machine.

Abstract: A processor communication register (PCR) contained in each processor within a multiprocessor system provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs, instantly allowing all of the other processors to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the multiprocessor system by providing processor communications to be immediately transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.

Abstract: A system and method for cache management in a data processing system having a memory hierarchy of upper memory and lower memory cache. A lower memory cache controller accesses a coherency state table to determine replacement policies of coherency states for cache lines present in the lower memory cache when receiving a cast-in request from one of the upper memory caches. The coherency state table implements a replacement policy that retains the more valuable cache coherency state information between the upper and lower memory caches for a particular cache line contained in both levels of memory at the time of cast-out from the upper memory cache.

Abstract: A method, system, and device for enabling intervention across same-level cache memories. In a preferred embodiment, responsive to a cache miss in a first cache memory a direct intervention request is sent from the first cache memory to a second cache memory requesting a direct intervention that satisfies the cache miss.

Abstract: A system and method for re-ordering store operations from a processor core to a store queue. When a store queue receives a new processor-issued store operation from the processor core, a store queue controller allocates a new entry in the store queue. In response to allocating the new entry in the store queue, the store queue controller determines whether or not the new entry is dependent on at least one other valid entry in the store queue. In response to determining the new entry is dependent on at least one other valid entry in the store queue, the store queue controller inhibits requesting of the new entry to the RC dispatch logic until each valid entry on which the new entry is dependent has been successfully dispatched to an RC machine by the RC dispatch logic.

Abstract: A method for determining the configuration of a digital design first obtains a set of latch values of a plurality of latches within the digital design. A setting of a Dial instance is then determined based upon the set of latch values by reference to a configuration database that specifies a mapping table uniquely associating each a plurality of different settings of the Dial with a respective one of a plurality of different sets of latch values. The setting of the Dial instance is then output. In one embodiment, the setting of the Dial is contained in a simulation setup file utilized to configure a simulation model to a state approximating the state of the digital design represented by the set of latch values.

Abstract: Methods, data processing systems, and program products supporting multi-cycle simulation are disclosed. According to one method, a configuration database including at least one data structure representing an instance of a Dial entity is received. The instance of the Dial entity has at least an input, an output, and at least one associated latch within a digital design. A value of the output of the instance of the Dial entity controls a value stored within the associated latch. A control file is also received. The control file indicates that at least one associated latch data structure is to be inserted within the configuration database to represent the latch during multi-cycle simulation.

Abstract: A method, data processing system, and program product for building an instrumented simulation model of a digital design are disclosed. According to the method, a model build tool locates, within design data collectively defining a simulation model of the digital design, a definition of a configuration construct specifying a relationship between values of one or more configuration latches within the digital design and settings of the configuration construct. In response to locating the definition of the configuration construct, the model build tool automatically creates an instrumentation entity within the design data. The instrumentation entity has one or more inputs logically coupled to the one or more configuration latches and one or more outputs for providing signals indicating characteristics of the configuration construct during simulation.

Abstract: In a method of compiling a simulation model of a digital design, a compiler receives an indication of a desired set of instrumentation entities to be included within a simulation model of a digital design described by a plurality of hierarchically arranged design entities. The instrumentation entities monitor logical operation of one or more of the plurality of design entities during simulation for occurrence of events of interest. In response to the indication, the compiler determines by reference to a bill-of-materials of a previously compiled file whether or not the previously compiled file was compiled with instrumentation entities compatible with the desired set of instrumentation entities. In response to determining that the previously compiled file was compiled with compatible instrumentation entities, the compiler compiles the simulation model of the digital design utilizing the previously compiled file in accordance with the indication.

Abstract: At a first cache memory affiliated with a first processor core, an exclusive memory access operation is received via an interconnect fabric coupling the first cache memory to second and third cache memories respectively affiliated with second and third processor cores. The exclusive memory access operation specifies a target address. In response to receipt of the exclusive memory access operation, the first cache memory detects presence or absence of a source indication indicating that the exclusive memory access operation originated from the second cache memory to which the first cache memory is coupled by a private communication network to which the third cache memory is not coupled. In response to detecting presence of the source indication, a coherency state field of the first cache memory that is associated with the target address is updated to a first data-invalid state.

Abstract: A processing unit for a multiprocessor data processing system includes a store-through upper level cache, an instruction sequencing unit that fetches instructions for execution, at least one instruction execution unit that executes a store-conditional instruction to determine a store target address, a store queue that, following execution of the store-conditional instruction, buffers a corresponding store operation, sequencer logic associated with the store queue. The sequencer logic, responsive to receipt of a latency indication indicating that resolution of the store-conditional operation as passing or failing is subject to significant latency, invalidates, prior to resolution of the store-conditional operation, a cache line in the store-through upper level cache to which a load-reserve operation previously bound.

Abstract: A multiprocessor data processing system includes a plurality of processors coupled to an interconnect and to a global promotion facility containing at least one promotion bit field. A first processor executes a high speed instruction sequence including a load-type instruction to acquire a promotion bit field within the global promotion facility exclusive of at least a second processor. The request may be made visible to all processors coupled to the interconnect. In response to execution of the load-type instruction, a register of the first processor receives a register bit field indicating whether or not the promotion bit field was acquired by execution of the load-type instruction. While the first processor holds the promotion bit field exclusive of the second processor, the second processor is permitted to initiate a request on the interconnect.

Abstract: In at least one hardware definition language (HDL) file, at least one design entity containing a functional portion of a digital system is specified. The design entity logically contains first and second latches each having a respective plurality of different possible latch values. With one or more statements, a first Dial instance is associated with the first latch and a second Dial instance is associated with the second latch. A setting of the first Dial instance thus controls which of the plurality of different possible values is loaded in the first latch, and a setting of the second Dial instance controls which of the plurality of different possible values is loaded in the second latch. With a statement, a Register instance is concurrently associated with both the first and the second latches, such that a setting of the Register instance controls the latch values loaded in both the first and second latches.

Abstract: A method and system for instrumenting testcase execution processing of a hardware description language (HDL) model using a simulation control program. In accordance with the method of the present invention, a set name application program interface (API) entry point is called wherein the set name API entry point includes program instructions for naming a simulation control program in association with testcase execution of the HDL model. A create event API entry point is called, wherein the create event API entry point includes an event identifier input parameter which identifies a testcase execution event with respect to the named simulation control program. In response to executing a testcase simulation cycle, signal values are retrieved from the HDL model into an instrumentation code block, wherein the instrumentation code block includes program instructions for processing the retrieved signals to detect whether the testcase execution event has occurred during the testcase simulation cycle.

Abstract: Disclosed herein is a method of storing data results of simulation processing of a hardware description language (HDL) model based upon keywords. In accordance with the method, result data obtained by simulation of at least one HDL model are received. In association with the result data, a plurality of value sets is received, where each value set includes at least one keyword having an associated value. Each keyword identifies a parameter external to the HDL model that affected the result data. The data results are stored within a data storage subsystem in association with the plurality of value sets such that particular result data are attributable to particular ones of the plurality of value sets. In one embodiment, a keyword table is built in the data storage system that indicates which data subdirectories store result data associated with particular value sets. The result data can then be queried based upon selected keywords of interest, for example, by reference to the keyword table.

Abstract: A processing unit for a multiprocessor data processing system includes a processor core including a store-through upper level cache, an instruction sequencing unit that fetches instructions for execution, a data register, and at least one instruction execution unit coupled to the instruction sequencing unit that concurrently executes multiple threads of instructions. The processor core, responsive to the at least one instruction execution unit executing a load-reserve instruction in a first thread that binds to a load target address in the store-through upper level cache during a reservation hazard window associated with a conflicting store-conditional operation of a second thread, causes a subsequent store-conditional operation of the first thread to a store target address matching the load target address to fail if the store-conditional operation of the second thread succeeds.

Abstract: A processing unit for a multiprocessor data processing system includes a processor core including a store-through upper level cache, an instruction sequencing unit that fetches instructions for execution, a data register, and at least one instruction execution unit. The instruction execution unit, responsive to receipt of a load-reserve instruction from the instruction sequencing unit, executes the load-reserve instruction to determine a load target address. The processor core, responsive to the execution of the load-reserve instruction, performs a corresponding load-reserve operation by accessing the store-through upper level cache utilizing the load target address to cause data associated with the load target address to be loaded from the store-through upper level cache into the data register and by establishing a reservation for a reservation granule including the load target address.