Abstract: A simulation control program receives a hardware description language (HDL) model including design entities and count event registers. Each count event registers is associated with a respective instance of an event. The count event registers include first and second registers for counting occurrences of a same replicated event generated within different instances of a same design entity having a same hierarchical level within the HDL model. The simulation control program also receives a correlation data structure indicating which count event registers are associated with instances of the same replicated event. During simulation processing, each of the count event registers maintains a respective count value representing a number of times an associated event instance occurs. The simulation control program sums count values of the first and second count event registers in accordance with the correlation data structure and outputs a count event data packet containing the aggregate count value.

Abstract: In at least one hardware definition language (HDL) file, a design entity containing a functional portion of a digital system is specified. The design entity logically contains a plurality of configuration latches each having multiple different possible latch values. The latch values of the plurality of configuration latches collectively define at least a portion of a configuration of the functional portion of the digital system. With a statement in the at least one HDL file, a read-only Dial entity is associated with the plurality of configuration latches. The read-only Dial has at least one output and a mapping table indicating a mapping between each of a plurality of possible output values that can be present at the output and a respective corresponding setting of the read-only Dial. The setting of the read-only Dial indicates which of a plurality of different possible configurations is represented by the latch values of the plurality of configuration latches.

Abstract: A configuration database associated with a digital design stores at least one data structure defining a Dial instance and a mapping between each possible input value of the Dial instance and a respective output value. The output value controls which of a number of different possible latch values is placed in a configuration latch to configure a functional portion of a simulation model of the digital design. The configuration database further indicates an association between the Dial instance and the configuration latch. In response to a request specifying an input value for the Dial instance, the data structure in the configuration database is accessed to determine an output value for the Dial instance based upon the mapping. In addition, a latch value for the configuration latch is obtained based upon the output value and the association indicated by the configuration database. The latch value is then utilized to set the configuration latch in the simulation model.

Abstract: A method and system for tracking instances of a testcase execution event within a hardware description language (HDL) model using a simulation control program. In accordance with the method of the present invention, a design entity list is generated within the HDL model, wherein the design entity list identifies all design entities instantiated within the HDL model. One or more instrumentation code modules are dynamically loaded into the simulation control program, wherein the instrumentation code modules generate and process testcase execution events associated with at least one of the identified design entities.

Abstract: A system configuration database is constructed in volatile memory by first determining which types of integrated circuits are present in a hardware system and the number of each type. In response to a determination, a system configuration database is loaded into volatile memory that includes a respective chip hardware database for each type of integrated circuit in the hardware system. Each chip hardware database defines a Dial entity controlling which of a plurality of different possible latch values is placed in a hardware latch of the associated type of integrated circuit. The system configuration database includes at least a first chip hardware database for a first type of integrated circuit that contains per-instance information for each of the multiple instances of the first type of integrated circuit within the hardware system.

Abstract: A method and system for associating instrumentation data with a simulation model within a batch simulation farm in which a simulation client communicates with an instrumentation server to process simulation data with respect to the simulation model. In accordance with the method of the present invention, an instrumentation eventlist is delivered from the simulation client to the instrumentation server. The eventlist contains instrumentation event information for the simulation model. Next, within the instrumentation server, a digital signature is computed that uniquely identifies contents of the instrumentation eventlist as being associated with the simulation model. Responsive to receiving simulation data from the simulation client, the digital signature is utilized to associate the simulation data with the simulation model.

Abstract: Methods, data processing systems, and program products are disclosed that support the definition and accessing of links indicating a relationship between configuration construct instances, such as Dial and Dial group instances, within a digital design. According to one method, first and second latches within the digital design are specified in at least one HDL statement within one or more HDL files representing the digital design. In the one or more HDL files, a first configuration construct instance referencing the first latch and a second configuration construct instance referencing the second latch are also defined. The first and second configuration construct instances provide interfaces through which values of the first and second latches can be accessed. In addition, a link indicating a relationship between the first and second configuration construct instances is also defined within the one or more HDL files.

Abstract: A method and system for minimizing redundancy in collected harvest event testcases from a batch simulation farm which includes a harvest testcase server that collects simulation data for a simulation model from at least one simulation client. In accordance with the method of the present invention, a testcase is executed on the simulation model within a simulation client. Responsive to the testcase triggering a harvest event, the harvest event is compared with a list of harvest events that have previously been triggered within the simulation model. In response to determining that the harvest event has not been previously triggered within the simulation model, the testcase is delivered to the harvest testcase server.

Abstract: A digital system includes a plurality of hierarchically arranged design entity instantiations including a first entity instantiation containing second and third instantiations of the same design entity. Each of the instantiations contains a respective instance of a configurable entity having a plurality of possible configuration values that each corresponds to a different configuration of a functional portion of the digital system. A configuration specification for the digital system is received including a Dial containing a mapping between each of a plurality of possible Dial input values and a respective one of a plurality of configuration values. The configuration specification generically refers to the design entity. In response to receipt of the configuration specification, both instance of the configurable entity are automatically located.

Abstract: A method is disclosed of associating a mapping function with a configuration construct of a digital design defined by one or more hardware description language (HDL) files. According to the method, in the HDL files, a configuration latch is specified within a design entity forming at least a portion of the digital design. In addition, a Dial is specified that defines a relationship between each of a plurality of input values and a respective one of a plurality of different output values. The HDL files also include a statement that instantiates an instance of the Dial in association with the configuration latch such that a one-to-one correspondence exists between a value contained within the configuration latch and an input value of the instance of the Dial. The HDL files further include a statement associating the Dial with a mapping function that applies a selected transformation to values read from or written to the instance of the Dial.

Abstract: A method and system for resolving testcase collection inconsistencies between a testcase list which includes testcases that have triggered harvest events within a simulation model, and a harvest hit table which records harvest events that have been triggered during simulation of the simulation model. First, the harvest hit table is updated from a simulation client to include a harvest event triggered by a testcase during simulation of the simulation model. The testcase is then collected within the testcase list. Finally, testcases identified within the testcase list are compared to testcases identified within the harvest hit table to determine inconsistencies therebetween.

Abstract: A method, system, and data structure for overriding a signal during model simulation. An override signal port is instantiated within a model for delivering an override signal from an instrumentation entity to a signal selection means, wherein the signal selection means selects between the signal and the override signal. A signal override is declared during model simulation, and in response to the declared signal override, the override signal is selected utilizing the signal selection means.

Abstract: A method and processor system that substantially enhances the store gathering capabilities of a store queue entry to enable gathering of a maximum number of proximate-in-time store operations before the entry is selected for dispatch. A counter is provided for each entry to track a time since a last gather to the entry. When a new gather does not occur before the counter reaches a threshold saturation point, the entry is signaled ready for dispatch. By defining an optimum threshold saturation point before the counter expires, sufficient time is provided for the entry to gather a proximate-in-time store operation. The entry may be deemed eligible for selection when certain conditions occur, including the entry becoming full, issuance of a barrier operation, and saturation of the counter. The use of the counter increases the ability of a store queue entry to complete gathering of enough store operations to update an entire cache line before that entry is dispatched to an RC machine.

Abstract: A method and system for providing centralized access to instrumentation count event information generated by simulation testing of a hardware simulation model, in which simulation testing is performed within a batch simulation farm by multiple simulation clients communicating with an instrumentation server. An entitylist that includes an identifier for each design entity within said hardware simulation model that has at least one instantiated instrumentation count event is generated within a simulation client. The entitylist is delivered from the simulation client to the instrumentation server. Within the instrumentation server, the entitylist is associated with an identifier for the hardware simulation model such that instrumentation count event information is accessible from said instrumentation server by individual design entity information.

Abstract: A method of processing a configuration of a digital system is disclosed. The digital system contains a configuration latch having a plurality of possible latch values that each corresponds to a different configuration of a functional portion of the digital system. The digital system further includes a signal coupled to an output of the configuration latch by a signal path. According to the method, a configuration specification for the digital system is received. The configuration specification includes a Dial mapping between each of a plurality of possible input values that can be received by the Dial and a respective one of a plurality of signal values for the signal. In response to receipt of the configuration specification, a number of inverting circuit elements within the signal path coupling the signal and the output of the configuration latch is determined.

Abstract: A method of specifying a configurable digital system is disclosed. According to the method, at least one design entity containing a functional portion of a digital system is specified in at least one hardware definition language (HDL) file. The design entity logically contains a configuration latch having a plurality of different possible configuration values that each corresponds to a different configuration of the functional portion of the digital system. A statement in the HDL file associates a Dial entity with the design entity. The Dial has a Dial input, a Dial output, and a mapping table indicating a mapping between each of a plurality of possible input values that can be received at the Dial input and a respective corresponding output value for the Dial output. The output value specifies which of the plurality of different possible configuration values is loaded into the configuration latch.

Abstract: The address tenure for PCR synchronization operations is redefined to support inclusion of the synchronization data within the address tenure. The bits of a particular field within the address tenure (e.g., the address field) are re-allocated to synchronization data, which is known to be small enough to fit within the unused bits. The address tenure is then broadcasted as a normal address operation and is snooped by all of the processors. The snooping logic is designed to recognize regular/normal address tenures and these modified address tenures and respond to a receipt of a modified address tenure by removing the synchronization data stored therein and updating the corresponding register location of the PCR.

Abstract: In at least one hardware definition language (HDL) file, at least one design entity containing a functional portion of a digital system is specified. The design entity logically contains a configuration latch having a plurality of different possible configuration values that each corresponds to a different configuration of the functional portion of the digital system. With a statement in the HDL file(s), a Dial entity is associated with the at least one design entity. The Dial has a Dial input, a Dial output, a mapping table indicating a mapping between each of a plurality of possible input values that can be received at the Dial input and a respective corresponding output value for the Dial output, and a default input value among the plurality of possible input values. The output value of the Dial entity controls which of the different possible configuration values is loaded in the configuration latch.

Abstract: In a configuration database, at least one latch data structure is created that corresponds to a hardware latch in a hardware system to be configured. The at least one latch data structure includes a method field indicating which of a plurality of different access methods can be used to access the hardware latch. In addition, the latch data structure includes at least one Dial data structure defining an instance of a Dial entity controlling which of a plurality of different possible latch values is placed in the hardware latch in response to each of a plurality of Dial settings. The configuration database further includes an association between the instance of the Dial entity and the hardware latch. The configuration database can then be referenced to set the hardware latch utilizing an access method indicated by the at least one latch data structure.

Abstract: A method of reducing errors in a cache memory of a computer system (e.g., an L2 cache) by periodically issuing a series of purge commands to the L2 cache, sequentially flushing cache lines from the L2 cache to an L3 cache in response to the purge commands, and correcting errors (single-bit) in the cache lines as they are flushed to the L3 cache. Purge commands are issued only when the processor cores associated with the L2 cache have an idle cycle available in a store pipe to the cache. The flush rate of the purge commands can be programmably set, and the purge mechanism can be implemented either in software running on the computer system, or in hardware integrated with the L2 cache. In the case of the software, the purge mechanism can be incorporated into the operating system. In the case of hardware, a purge engine can be provided which advantageously utilizes the store pipe that is provided between the L1 and L2 caches.