Patents by Inventor Derek J. Gochnour

Derek J. Gochnour has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6691696
    Abstract: A semiconductor wafer saw for dicing semiconductor wafers comprises variable lateral indexing capabilities and multiple blades. The wafer saw, because of its variable indexing capabilities, can dice wafers having a plurality of differently sized semiconductor devices thereon into their respective discrete components. In addition, the wafer saw with its multiple blades, some of which may be independently laterally or vertically movable relative to other blades, can more efficiently dice silicon wafers into individual semiconductor devices.
    Type: Grant
    Filed: October 17, 2001
    Date of Patent: February 17, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, Derek J. Gochnour, Michael E. Hess, David R. Hembree
  • Patent number: 6687990
    Abstract: A semiconductor wafer saw and method of using the same for dicing semiconductor wafers comprising a wafer saw including variable lateral indexing capabilities and multiple blades are disclosed. The wafer saw, because of its variable indexing capabilities, can dice wafers having a plurality of differently sized semiconductor devices thereon into their respective discrete components. In addition, the wafer saw with its multiple blades, some of which may be independently laterally or vertically movable relative to other blades, can more efficiently dice silicon wafers into individual semiconductor devices. The wafer saw may also be used to simultaneously sever and electrically isolate conductive traces that extend over adjacent semiconductor devices from connective lines therefor.
    Type: Grant
    Filed: August 20, 2002
    Date of Patent: February 10, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, Derek J. Gochnour, Michael E. Hess, David R. Hembree
  • Publication number: 20040011283
    Abstract: A method and apparatus for preventing board warpage during the application and curing or drying of liquid epoxies, or the like, on printed circuit boards using a clamping fixture assembly, which includes at least one clamping fixture support and at least one clamping fixture overlay. If desired, a plurality of printed circuit boards may be processed using an appropriate clamping fixture assembly. Furthermore, the clamping fixture may be constructed so a slight bow or curvature thereof can counter either a convex or concave bow or curvature of the printed circuit board.
    Type: Application
    Filed: July 14, 2003
    Publication date: January 22, 2004
    Inventors: Derek J. Gochnour, Leonard E. Mess
  • Publication number: 20040009708
    Abstract: An apparatus and method of removably interconnecting a reduced-sized memory card with an extension member. The locking mechanism may be formed in a peripheral end portion of the reduced-sized memory card that may include an entry surface and a ledge. The extension member may include a biasing portion that slidably engages the entry surface and removable interconnects with the ledge. With this arrangement, the extension member may easily be secured and removed from the reduced-sized memory card, allowing easy interchangeability between a standard-sized socket of one electronic device and a reduced-sized socket of another electronic device.
    Type: Application
    Filed: July 9, 2002
    Publication date: January 15, 2004
    Inventors: Derek J. Gochnour, Walter L. Moden, Michael W. Morrison
  • Patent number: 6631662
    Abstract: A semiconductor wafer saw and method of using the same for dicing semiconductor wafers are disclosed comprising a wafer saw including variable lateral indexing capabilities and multiple blades. The wafer saw, because of its variable indexing capabilities, can dice wafers having a plurality of differently sized semiconductor devices thereon into their respective discrete components. In addition, the wafer saw with its multiple blades, some of which may be independently laterally or vertically movable relative to other blades, can more efficiently dice silicon wafers into individual semiconductor devices.
    Type: Grant
    Filed: May 22, 2001
    Date of Patent: October 14, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, Derek J. Gochnour, Michael E. Hess, David R. Hembree
  • Publication number: 20030191550
    Abstract: An inventive method in an integrated circuit (IC) manufacturing process for using data regarding repair procedures conducted on IC's at probe to determine whether any further repairs will be conducted later in the manufacturing process includes storing the data in association with a fuse ID of each of the IC's. The ID codes of the IC's are automatically read, for example, at an opens/shorts test during the manufacturing process. The data stored in association with the ID codes of the IC's is then accessed, and additional repair procedures the IC's may undergo are selected in accordance with the accessed data. Thus, for example, the accessed data may indicate that an IC is unrepairable, so the IC can proceed directly to a scrap bin without having to be queried to determine whether it is repairable, as is necessary in traditional IC manufacturing processes.
    Type: Application
    Filed: March 27, 2003
    Publication date: October 9, 2003
    Inventors: Salman Akram, Warren M. Farnworth, Derek J. Gochnour, David R. Hembree, Michael E. Hess, John O. Jacobson, James M. Wark, Alan G. Wood
  • Patent number: 6630836
    Abstract: A BGA test socket for use in standard testing and burn-in testing of BGA dice and method for testing such dice is disclosed wherein a die contact insert made of silicon or ceramic using standard IC fabrication technology is used. Through using such an insert, even small scale (pitch) BGA dice can be reliably tested including chip scale packaged (“CSP”) BGA dice. Furthermore, using such an insert allows a conventional socket to be adapted for use with a wide variety of both BGA dice and other varieties. A method for using the device is disclosed which overcomes current static electricity problems experienced in testing CSP BGA dice through closing the test socket before removing the die deposit probe.
    Type: Grant
    Filed: August 26, 2002
    Date of Patent: October 7, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Derek J. Gochnour, David R. Hembree
  • Patent number: 6628128
    Abstract: A BGA test socket for use in standard testing and burn-in testing of BGA dies and method for testing such dies is disclosed wherein a die contact insert made of silicon or ceramic using standard IC fabrication technology is used. Through using such an insert, even small scale (pitch) BGA dies can be reliably tested including chip scale packaged (“CSP”) BGA dies. Furthermore, using such an insert allows a conventional socket to be adapted for use with a wide variety of both BGA dies and other varieties. A method for using the device is disclosed which overcomes current static electricity problems experienced in testing CSP BGA dies through closing the test socket before removing the die deposit probe.
    Type: Grant
    Filed: August 30, 2000
    Date of Patent: September 30, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Derek J. Gochnour, David R. Hembree
  • Publication number: 20030162311
    Abstract: A method for fabricating semiconductor die packages including a mounting substrate and dice attached thereto. The mounting substrate includes multiple die attach sites and a designator having substrate identification information. The die attach sites are evaluated and categorized as either good or defective die attach sites, wherein the evaluated information is saved in an electronic file as mapped information. A die is attached to the die attach sites in accord with the information, wherein known good dice are attached to the good die attach sites and known defective dice are attached to the defective die attach sites. The assembly is then encapsulated in a transfer molding operation.
    Type: Application
    Filed: April 25, 2003
    Publication date: August 28, 2003
    Inventors: Warren M. Farnworth, Derek J. Gochnour
  • Patent number: 6592670
    Abstract: A method and apparatus for preventing board warpage during the application and curing or drying of liquid epoxies, or the like, on printed circuit boards using a clamping fixture assembly, which includes at least one clamping fixture support and at least one clamping fixture overlay. If desired, a plurality of printed circuit boards may be processed using an appropriate clamping fixture assembly. Furthermore, the clamping fixture may be constructed so a slight bow or curvature thereof can counter either a convex or concave bow or curvature of the printed circuit board. In the method at least one printed circuit board is mounted to a clamping fixture support whereby a clamping fixture overlay is placed on top of the first printed circuit board.
    Type: Grant
    Filed: May 24, 2000
    Date of Patent: July 15, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Derek J. Gochnour, Leonard E. Mess
  • Publication number: 20030111766
    Abstract: A method and apparatus for preventing board warpage during the application and curing or drying of liquid epoxies, or the like, on printed circuit boards using a clamping fixture assembly, which includes at least one clamping fixture support and at least one clamping fixture overlay. If desired, a plurality of printed circuit boards may be processed using an appropriate clamping fixture assembly. Furthermore, the clamping fixture may be constructed so a slight bow or curvature thereof can counter either a convex or concave bow or curvature of the printed circuit board.
    Type: Application
    Filed: February 5, 2003
    Publication date: June 19, 2003
    Inventors: Derek J. Gochnour, Leonard E. Mess
  • Patent number: 6578458
    Abstract: A semiconductor wafer saw and method of using the same for dicing semiconductor wafers comprising a wafer saw including variable lateral indexing capabilities and multiple blades. The wafer saw, because of its variable indexing capabilities, can dice wafers having a plurality of differently sized semiconductor devices thereon into their respective discrete components. In addition, the wafer saw with its multiple blades, some of which may be independently laterally or vertically movable relative to other blades, can more efficiently dice silicon wafers into individual semiconductor devices.
    Type: Grant
    Filed: March 18, 2002
    Date of Patent: June 17, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, Derek J. Gochnour, Michael E. Hess, David R. Hembree
  • Patent number: 6555400
    Abstract: A method and apparatus relating to fabricating semiconductor die packages including a mounting substrate and dice attached thereto. The mounting substrate includes multiple die attach sites and a designator having substrate identification information. The die attach sites are evaluated and categorized as either good or defective die attach sites, wherein the evaluated information is saved in an electronic file as mapped information. A die attach apparatus attaches dice to the die attach sites in accord with the mapped information, wherein known good dice are attached to the good die attach sites and known defective dice are attached to the defective die attach sites. The assembly is then encapsulated in a transfer molding operation. Since each die attach site includes a die attached thereto, the structural integrity of the mounting substrate is maintained and there is greater volume control of encapsulation material in the transfer molding operation to prevent waste and shortage of the encapsulation material.
    Type: Grant
    Filed: August 22, 2001
    Date of Patent: April 29, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Derek J. Gochnour
  • Patent number: 6553276
    Abstract: An inventive method in an integrated circuit (IC) manufacturing process for using data regarding repair procedures conducted on IC's at probe to determine whether any further repairs will be conducted later in the manufacturing process includes storing the data in association with a fuse ID of each of the IC's. The ID codes of the IC's are automatically read, for example, at an opens/shorts test during the manufacturing process. The data stored in association with the ID codes of the IC's is then accessed, and additional repair procedures the IC's may undergo are selected in accordance with the accessed data. Thus, for example, the accessed data may indicate that an IC is unrepairable, so the IC can proceed directly to a scrap bin without having to be queried to determine whether it is repairable, as is necessary in traditional IC manufacturing processes.
    Type: Grant
    Filed: February 5, 2002
    Date of Patent: April 22, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, Warren M. Farnworth, Derek J. Gochnour, David R. Hembree, Michael E. Hess, John O Jacobson, James M. Wark, Alan G. Wood
  • Publication number: 20030047805
    Abstract: A method and apparatus relating to fabricating semiconductor die packages including a mounting substrate and dice attached thereto. The mounting substrate includes multiple die attach sites and a designator having substrate identification information. The die attach sites are evaluated and categorized as either good or defective die attach sites, wherein the evaluated information is saved in an electronic file as mapped information. A die attach apparatus attaches dice to the die attach sites in accord with the mapped information, wherein known good dice are attached to the good die attach sites and known defective dice are attached to the defective die attach sites. The assembly is then encapsulated in a transfer molding operation.
    Type: Application
    Filed: October 25, 2002
    Publication date: March 13, 2003
    Inventors: Warren M. Farnworth, Derek J. Gochnour
  • Publication number: 20030046810
    Abstract: A method and apparatus relating to fabricating semiconductor die packages including a mounting substrate and dice attached thereto. The mounting substrate includes multiple die attach sites and a designator having substrate identification information. The die attach sites are evaluated and categorized as either good or defective die attach sites, wherein the evaluated information is saved in an electronic file as mapped information. A die attach apparatus attaches dice to the die attach sites in accord with the mapped information, wherein known good dice are attached to the good die attach sites and known defective dice are attached to the defective die attach sites. The assembly is then encapsulated in a transfer molding operation.
    Type: Application
    Filed: October 25, 2002
    Publication date: March 13, 2003
    Inventors: Warren M. Farnworth, Derek J. Gochnour
  • Patent number: 6527999
    Abstract: A method and apparatus for preventing board warpage during the application and curing or drying of liquid epoxies, or the like, on printed circuit boards using a clamping fixture assembly, which includes at least one clamping fixture support and at least one clamping fixture overlay. If desired, a plurality of printed circuit boards may be processed using an appropriate clamping fixture assembly. Furthermore, the clamping fixture may be constructed so a slight bow or curvature thereof can counter either a convex or concave bow or curvature of the printed circuit board.
    Type: Grant
    Filed: April 13, 2001
    Date of Patent: March 4, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Derek J. Gochnour, Leonard E. Mess
  • Publication number: 20030038365
    Abstract: A method and apparatus relating to fabricating semiconductor die packages including a mounting substrate and dice attached thereto. The mounting substrate includes multiple die attach sites and a designator having substrate identification information. The die attach sites are evaluated and categorized as either good or defective die attach sites, wherein the evaluated information is saved in an electronic file as mapped information. A die attach apparatus attaches dice to the die attach sites in accord with the mapped information, wherein known good dice are attached to the good die attach sites and known defective dice are attached to the defective die attach sites. The assembly is then encapsulated in a transfer molding operation. Since each die attach site includes a die attached thereto, the structural integrity of the mounting substrate is maintained and there is greater volume control of encapsulation material in the transfer molding operation to prevent waste and shortage of the encapsulation material.
    Type: Application
    Filed: August 22, 2001
    Publication date: February 27, 2003
    Inventors: Warren M. Farnworth, Derek J. Gochnour
  • Publication number: 20030030122
    Abstract: A semiconductor wafer saw and method of using the same for dicing semiconductor wafers comprising a wafer saw including variable lateral indexing capabilities and multiple blades. The wafer saw, because of its variable indexing capabilities, can dice wafers having a plurality of differently sized semiconductor devices thereon into their respective discrete components. In addition, the wafer saw with its multiple blades, some of which may be independently laterally or vertically movable relative to other blades, can more efficiently dice silicon wafers into individual semiconductor devices.
    Type: Application
    Filed: October 1, 2002
    Publication date: February 13, 2003
    Inventors: Salman Akram, Derek J. Gochnour, Michael E. Hess, David R. Hembree
  • Publication number: 20030011393
    Abstract: A BGA test socket for use in standard testing and burn-in testing of BGA dies and method for testing such dies is disclosed wherein a die contact insert made of silicon or ceramic using standard IC fabrication technology is used. Through using such an insert, even small scale (pitch) BGA dies can be reliably tested including chip scale packaged (“CSP”) BGA dies. Furthermore, using such an insert allows a conventional socket to be adapted for use with a wide variety of both BGA dies and other varieties. A method for using the device is disclosed which overcomes current static electricity problems experienced in testing CSP BGA dies through closing the test socket before removing the die deposit probe.
    Type: Application
    Filed: August 27, 2002
    Publication date: January 16, 2003
    Inventors: Warren M. Farnworth, Derek J. Gochnour, David R. Hembree