Patents by Inventor Derek J. Gochnour

Derek J. Gochnour has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6255196
    Abstract: A semiconductor wafer saw and method of using the same for dicing semiconductor wafers comprising a wafer saw including variable lateral indexing capabilities and multiple blades. The wafer saw, because of its variable indexing capabilities, can dice wafers having a plurality of differently sized semiconductor devices thereon into their respective discrete components. In addition, the wafer saw with its multiple blades, some of which may be independently laterally or vertically movable relative to other blades, can more efficiently dice silicon wafers into individual semiconductor devices.
    Type: Grant
    Filed: May 9, 2000
    Date of Patent: July 3, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, Derek J. Gochnour, Michael E. Hess, David R. Hembree
  • Patent number: 6250192
    Abstract: A semiconductor wafer saw and method of using the same for dicing semiconductor wafers are disclosed comprising a wafer saw including variable lateral indexing capabilities and multiple blades. The wafer saw, because of its variable indexing capabilities, can dice wafers having a plurality of differently sized semiconductor devices thereon into their elective discrete components. In addition, the wafer saw with its multiple blades, some of which may be independently laterally or vertically movable relative to other blades, can more efficiently dice silicon wafers into individual semiconductor devices.
    Type: Grant
    Filed: November 12, 1996
    Date of Patent: June 26, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, Derek J. Gochnour, Michael E. Hess, David R. Hembree
  • Patent number: 6247629
    Abstract: A wire bond monitoring system for monitoring wire bonds made on layered packages includes a technique for accessing both the die and the laminate package and making electrical contact thereto so as to test the continuity of the wire bond connection. An electrical connection can be made to a metal trace between the die and the laminate package by contacting a via extending downwardly through the package. Alternatively, a contact may be made from above using a flexible contact. The flexible contact may be attached to the wire bond clamp.
    Type: Grant
    Filed: February 5, 1999
    Date of Patent: June 19, 2001
    Assignee: Micron Technology, Inc.
    Inventors: John O. Jacobson, Derek J. Gochnour, Steven G. Thummel
  • Patent number: 6224936
    Abstract: A method for preventing board warpage during the application and curing or drying of liquid epoxies, or the like, on printed circuit boards using a clamping fixture assembly, which includes at least one clamping fixture support and at least one clamping fixture overlay. If desired, a plurality of printed circuit boards may be processed using an appropriate clamping fixture assembly. Furthermore, the clamping fixture may be constructed so a slight bow or curvature thereof can counter either a convex or concave bow or curvature of the printed circuit board.
    Type: Grant
    Filed: October 7, 1998
    Date of Patent: May 1, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Derek J. Gochnour, Leonard E. Mess
  • Patent number: 6196096
    Abstract: A semiconductor wafer saw and method of using the same for dicing semiconductor wafers comprising a wafer saw including variable lateral indexing capabilities and multiple blades. The wafer saw, because of its variable indexing capabilities, can dice wafers having a plurality of differently sized semiconductor devices thereon into their respective discrete components. In addition, the wafer saw with its multiple blades, some of which may be independently laterally or vertically movable relative to other blades, can more efficiently dice silicon wafers into individual semiconductor devices.
    Type: Grant
    Filed: November 4, 1999
    Date of Patent: March 6, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, Derek J. Gochnour, Michael E. Hess, David R. Hembree
  • Patent number: 6180527
    Abstract: A method for thinning articles, such as wafers in an IC product, includes applying a reference layer to a first surface of the article to be thinned; removing a portion of the reference layer from its exposed surface to provide a reference surface; and thinning the article by removing a portion of the article from its second surface to provide a thinned surface. The orientation of the reference surface relative to the second surface is controlled, and the orientation of the thinned surface relative to the reference surface is controlled. There are also provided apparatuses and systems which are suitable for use in such methods, as well as intermediate articles and finished products containing articles formed in such methods.
    Type: Grant
    Filed: August 9, 1999
    Date of Patent: January 30, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Derek J. Gochnour
  • Patent number: 6155247
    Abstract: A semiconductor wafer saw and method of using the same for dicing semiconductor wafers comprising a wafer saw including variable lateral indexing capabilities and multiple blades. The wafer saw, because of its variable indexing capabilities, can dice wafers having a plurality of differently sized semiconductor devices thereon into their respective discrete components. In addition, the wafer saw with its multiple blades, some of which may be independently laterally or vertically movable relative to other blades, can more efficiently dice silicon wafers into individual semiconductor devices.
    Type: Grant
    Filed: March 17, 1999
    Date of Patent: December 5, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, Derek J. Gochnour, Michael E. Hess, David R. Hembree
  • Patent number: 6119675
    Abstract: A semiconductor wafer saw and method of using the same for dicing semiconductor wafers comprising a wafer saw including variable lateral indexing capabilities and multiple blades. The wafer saw, because of its variable indexing capabilities, can dice wafers having a plurality of differently sized semiconductor devices thereon into their respective discrete components. In addition, the wafer saw with its multiple blades, some of which may be independently laterally or vertically movable relative to other blades, can more efficiently dice silicon wafers into individual semiconductor devices.
    Type: Grant
    Filed: April 29, 1998
    Date of Patent: September 19, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, Derek J. Gochnour, Michael E. Hess, David R. Hembree
  • Patent number: 6085962
    Abstract: A wire bond monitoring system for monitoring wire bonds made on layered packages includes a technique for accessing both the die and the laminate package and making electrical contact thereto so as to test the continuity of the wire bond connection. An electrical connection can be made to a metal trace between the die and the laminate package by contacting a via extending downwardly through the package. Alternatively, a contact may be made from above using a flexible contact. The flexible contact may be attached to the wire bond clamp.
    Type: Grant
    Filed: September 8, 1997
    Date of Patent: July 11, 2000
    Assignee: Micron Technology, Inc.
    Inventors: John O. Jacobson, Derek J. Gochnour, Steven G. Thummel
  • Patent number: 6006739
    Abstract: A semiconductor wafer saw and method of using the same for dicing semiconductor wafers comprising a wafer saw including variable lateral indexing capabilities and multiple blades. The wafer saw, because of its variable indexing capabilities, can dice wafers having a plurality of differently sized semiconductor devices thereon into their respective discrete components. In addition, the wafer saw with its multiple blades, some of which may be independently laterally or vertically movable relative to other blades, can more efficiently dice silicon wafers into individual semiconductor devices.
    Type: Grant
    Filed: March 17, 1999
    Date of Patent: December 28, 1999
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, Derek J. Gochnour, Michael E. Hess, David R. Hembree
  • Patent number: 5907492
    Abstract: An inventive method in an integrated circuit (IC) manufacturing process for using data regarding repair procedures conducted on IC's at probe to determine whether any further repairs will be conducted later in the manufacturing process includes storing the data in association with a fuse ID of each of the IC's. The ID codes of the IC's are automatically read, for example, at an opens/shorts test during the manufacturing process. The data stored in association with the ID codes of the IC's is then accessed, and additional repair procedures the IC's may undergo are selected in accordance with the accessed data. Thus, for example, the accessed data may indicate that an IC is unrepairable, so the IC can proceed directly to a scrap bin without having to be queried to determine whether it is repairable, as is necessary in traditional IC manufacturing processes.
    Type: Grant
    Filed: June 6, 1997
    Date of Patent: May 25, 1999
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, Warren M. Farnworth, Derek J. Gochnour, David R. Hembree, Michael E. Hess, John O. Jacobson, James M. Wark, Alan G. Wood
  • Patent number: 5342807
    Abstract: On a semiconductor integrated circuit die, a semipermanent electrical connection is effected by the use of wirebond techniques, in which the parameters of the wirebond are controlled, so that less bonding force retains the leadwires to the bondpads than the attachment strength of the bondpads to the die. The wirebond techniques include attaching leadwires to bondpads on the die, using ultrasonic wedge bonding. The strength of the bond between the leadwires is significantly less than the attachment strength of the bondpads, preferably by a ratio which ensures that the bondpads are not lifted from the die when the leadwires are removed by breaking the bond between the leadwires and the bondpads. Subsequent to testing and burnin, the bond between the leadwires and the bondpads is severed. The die are then removed from the package body and the bondpads may then be attached by conventional means. The technique is useful in providing known good die.
    Type: Grant
    Filed: November 13, 1992
    Date of Patent: August 30, 1994
    Assignee: Micron Technology, Inc.
    Inventors: Larry D. Kinsman, Derek J. Gochnour, Alan G. Wood, Warren M. Farnworth
  • Patent number: 5336649
    Abstract: In order to provide pretested bare semiconductor integrated circuit die, a temporary mechanical connection is effected by the use of a soluble material. A semipermanent electrical connection is effected, in which the parameters of the connection are controlled, so that the die remains functional subsequent to burnin and test. Subsequent to testing and burnin, the die are removed from the package body. The technique is useful in providing known good die.
    Type: Grant
    Filed: November 13, 1992
    Date of Patent: August 9, 1994
    Assignee: Micron Technology, Inc.
    Inventors: Larry D. Kinsman, Derek J. Gochnour, Alan G. Wood, Warren M. Farnworth
  • Patent number: 5173451
    Abstract: On a semiconductor integrated circuit die, a semipermanent electrical connection is effected by the use of wirebond techniques, in which the parameters of the wirebond are controlled, so that less bonding force retains the leadwires to the bondpads than the attachment strength of the bondpads to the die. The wirebond techniques include attaching leadwires to bondpads on the die, using ultrasonic wedge bonding. The strength of the bond between the leadwires is significantly less than the attachment strength of the bondpads, preferably by a ratio which ensures that the bondpads are not lifted from the die when the leadwires are removed by breaking the bond between the leadwires and the bondpads. Subsequent to testing and burnin, the bond between the leadwires and the bondpads is severed. The die are then removed from the die cavity plate and the bondpads may then be attached by conventional means. The technique is useful in providing known good die.
    Type: Grant
    Filed: May 26, 1992
    Date of Patent: December 22, 1992
    Assignee: Micron Technology, Inc.
    Inventors: Larry D. Kinsman, Derek J. Gochnour