Patents by Inventor Desi Rhoden
Desi Rhoden has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180196764Abstract: A computing module includes an interface to asynchronously, serially exchange parallel system bus data with one or more other modules of a computer system that includes the computing module. The computing module can asynchronously, serially transfer first parallel bus data to another module of the computer system, and can asynchronously, serially receive second parallel bus data from another module of the computer system.Type: ApplicationFiled: July 25, 2017Publication date: July 12, 2018Inventors: Frank W. Ahern, Desi Rhoden, Jeff Doss, Charles Mollo
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Publication number: 20170075830Abstract: A computing module includes an interface to asynchronously, serially exchange parallel system bus data with one or more other modules of a computer system that includes the computing module. The computing module can asynchronously, serially transfer first parallel bus data to another module of the computer system, and can asynchronously, serially receive second parallel bus data from another module of the computer system.Type: ApplicationFiled: November 28, 2016Publication date: March 16, 2017Inventors: Frank W. Ahern, Desi Rhoden, Jeff Doss, Charles Mollo
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Patent number: 9535454Abstract: A computing module includes an interface to asynchronously, serially exchange parallel system bus data with one or more other modules of a computer system that includes the computing module. The computing module can asynchronously, serially transfer first parallel bus data to another module of the computer system, and can asynchronously, serially receive second parallel bus data from another module of the computer system.Type: GrantFiled: October 16, 2012Date of Patent: January 3, 2017Assignee: INTELLECTUAL VENTURES I LLCInventors: Frank W. Ahern, Desi Rhoden, Jeff Doss, Charles Mollo
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Publication number: 20130042046Abstract: A computing module includes an interface to asynchronously, serially exchange parallel system bus data with one or more other modules of a computer system that includes the computing module. The computing module can asynchronously, serially transfer first parallel bus data to another module of the computer system, and can asynchronously, serially receive second parallel bus data from another module of the computer system.Type: ApplicationFiled: October 16, 2012Publication date: February 14, 2013Inventors: Frank W. Ahern, Desi Rhoden, Jeff Doss, Charles Mollo
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Patent number: 8291140Abstract: A computing module includes an interface to asynchronously, serially exchange parallel system bus data with one or more other modules of a computer system that includes the computing module. The computing module can asynchronously, serially transfer first parallel bus data to another module of the computer system, and can asynchronously, serially receive second parallel bus data from another module of the computer system.Type: GrantFiled: September 22, 2011Date of Patent: October 16, 2012Inventors: Frank W. Ahern, Desi Rhoden, Jeff Doss, Charles Mollo
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Publication number: 20120017023Abstract: A computing module includes an interface to asynchronously, serially exchange parallel system bus data with one or more other modules of a computer system that includes the computing module. The computing module can asynchronously, serially transfer first parallel bus data to another module of the computer system, and can asynchronously, serially receive second parallel bus data from another module of the computer system.Type: ApplicationFiled: September 22, 2011Publication date: January 19, 2012Inventors: Frank W. Ahern, Desi Rhoden, Jeff Doss, Charles Mollo
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Patent number: 8060675Abstract: A computing module includes an interface to asynchronously, serially exchange parallel system bus data with one or more other modules of a computer system that includes the computing module. The computing module can asynchronously, serially transfer first parallel bus data to another module of the computer system, and can asynchronously, serially receive second parallel bus data from another module of the computer system.Type: GrantFiled: December 22, 2009Date of Patent: November 15, 2011Inventors: Frank Ahern, Desi Rhoden, Jeff Doss, Charles Mollo
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Patent number: 7734852Abstract: A modular computer system (20) including a universal connectivity station (UCS) (22) interconnected to a plurality of remote modules (30, 32, 34, 36, 38, 42) via a plurality of respective high speed serial links (26, 40) such as based on proprietary Split-Bridge™ technology. The plurality modules, including a processor module (42) which may include core parts including a CPU, memory, AGP Graphics, and system bus interface may be remotely located from each of the other modules, including the UCS (22). The present invention achieves technical advantages wherein each module of the modular computer system (20) appear to each device to be interconnected to the other on a parallel bus since the high speed serial links appear transparent. Preferably, although not necessary, each of the modules including the UCS 22 are based on the PCI bus architecture, or the PCMCIA bus architecture, although other bus architectures are well suited to be incorporated using the present invention.Type: GrantFiled: April 27, 2000Date of Patent: June 8, 2010Inventors: Frank W. Ahern, Desi Rhoden, Jeff Doss, Charles Mollo
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Publication number: 20100100650Abstract: A computing module includes an interface to asynchronously, serially exchange parallel system bus data with one or more other modules of a computer system that includes the computing module. The computing module can asynchronously, serially transfer first parallel bus data to another module of the computer system, and can asynchronously, serially receive second parallel bus data from another module of the computer system.Type: ApplicationFiled: December 22, 2009Publication date: April 22, 2010Inventors: Frank W. Ahern, Desi Rhoden, Jeff Doss, Charles Mollo
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Patent number: 7657678Abstract: A modular computer system (20) including a universal connectivity station (UCS) (22) interconnected to a plurality of remote modules (30, 32, 34, 36, 38, 42) via a plurality of respective high speed serial links (26, 40) such as based on proprietary Split-Bridge™ technology. The plurality modules, including a processor module (42) which may include core parts including a CPU, memory, AGP Graphics, and system bus interface may be remotely located from each of the other modules, including the UCS (22). The present invention achieves technical advantages wherein each module of the modular computer system (20) appear to each device to be interconnected to the other on a parallel bus since the high speed serial links appear transparent. Preferably, although not necessary, each of the modules including the UCS 22 are based on the PCI bus architecture, or the PCMCIA bus architecture, although other bus architectures are well suited to be incorporated using the present invention.Type: GrantFiled: December 13, 2005Date of Patent: February 2, 2010Inventors: Frank W. Ahern, Desi Rhoden, Jeff Doss, Charles Mollo
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Publication number: 20060288141Abstract: A modular computer system (20) including a universal connectivity station (UCS) (22) interconnected to a plurality of remote modules (30, 32, 34, 36, 38, 42) via a plurality of respective high speed serial links (26, 40) such as based on proprietary Split-Bridge™ technology. The plurality modules, including a processor module (42) which may include core parts including a CPU, memory, AGP Graphics, and system bus interface may be remotely located from each of the other modules, including the UCS (22). The present invention achieves technical advantages wherein each module of the modular computer system (20) appear to each device to be interconnected to the other on a parallel bus since the high speed serial links appear transparent. Preferably, although not necessary, each of the modules including the UCS 22 are based on the PCI bus architecture, or the PCMCIA bus architecture, although other bus architectures are well suited to be incorporated using the present invention.Type: ApplicationFiled: August 31, 2006Publication date: December 21, 2006Inventors: Frank Ahern, Desi Rhoden, Jeff Doss, Charles Mollo
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Publication number: 20060095616Abstract: A modular computer system (20) including a universal connectivity station (UCS) (22) interconnected to a plurality of remote modules (30, 32, 34, 36, 38, 42) via a plurality of respective high speed serial links (26, 40) such as based on proprietary Split-Bridge™ technology. The plurality modules, including a processor module (42) which may include core parts including a CPU, memory, AGP Graphics, and system bus interface may be remotely located from each of the other modules, including the UCS (22). The present invention achieves technical advantages wherein each module of the modular computer system (20) appear to each device to be interconnected to the other on a parallel bus since the high speed serial links appear transparent. Preferably, although not necessary, each of the modules including the UCS 22 are based on the PCI bus architecture, or the PCMCIA bus architecture, although other bus architectures are well suited to be incorporated using the present invention.Type: ApplicationFiled: December 13, 2005Publication date: May 4, 2006Inventors: Frank Ahern, Desi Rhoden, Jeff Doss, Charles Mollo
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Publication number: 20050021870Abstract: A modular computer system (20) including a universal connectivity station (UCS) (22) having a processor (42) interconnecting a plurality of physically remote modules including a PDA (36) and Smartphone (38), and a display (34). Each module of the modular computer system (20) appear to each device to be interconnected to the other. The UCS (22) enables the PDA (36) and Smartphone (38) to drive the display (38). The UCS (22) is also connectable to a data network via a network interface (54). External control devices including a keyboard (50) and mouse (52) may also control the UCS (22). The UCS (22) may translate the keyboard inputs to keystrokes, and mouse movements clicks to cursor movements and stylus taps for visually rendering on the PDA and Smartphone.Type: ApplicationFiled: February 19, 2004Publication date: January 27, 2005Inventors: Jason Carnahan, Paul Moreton, Frank Ahern, Desi Rhoden, Jeff Doss, Charles Mollo
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Publication number: 20040230668Abstract: A modular computer system (20) including a universal connectivity station (UCS) (22) having a processor (42) interconnecting a plurality of physically remote modules including a PDA (36) and Smartphone (38), and a display (34). Each module of the modular computer system (20) appear to each device to be interconnected to the other. The UCS (22) enables the PDA (36) and Smartphone (38) to drive the display (38). External control devices including a keyboard (50) and mouse (52) may also control the UCS (22). The UCS (22) may translate the keyboard inputs to keystrokes, and mouse movements clicks to cursor movements and stylus taps for visually rendering on the PDA and Smartphone.Type: ApplicationFiled: January 28, 2004Publication date: November 18, 2004Inventors: Jason Carnahan, Paul Moreton, Frank Ahern, Desi Rhoden, Jeff Doss, Charles Mollo
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Patent number: 6782466Abstract: A memory access approach optimizes memory address mapping for accessing data in a virtual memory arrangement wherein multiple banks of data are opened at once. One specific implementation is directed to a process of accessing data in a plurality of addressable banks of memory cells. The process involves accessing the memory cells by addressing arrays in the banks via column and row bits, and directing the address and control signals so that the addressable column address and row address bits are selected with a lower order group of the address bits directed to select the column address bits, and the next highest group of the address bits directed to select bank address bits. The next highest group of the address bits are directed to select the row address bits.Type: GrantFiled: November 24, 1999Date of Patent: August 24, 2004Assignee: Koninklijke Philips Electronics N.V.Inventors: James Crawford Steele, Desi Rhoden, George Crouse
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Publication number: 20030126356Abstract: A SLDRAM System is provided with a plurality of in-circuit, calibratable memory modules and a memory controller for issuing unicast and multicast command packets to the memory modules. Command packets are transmitted over a unidirectional command link that includes a complementary pair of command clock lines, a command FLAG line and a plurality of noncomplemented command bit lines. Each of the command clock lines, command bit lines and the FLAG line is a SLIO transmission line. Data transfer operations are carried out in response to the command packets over one or more bidirectional data links that each includes two complementary pairs of data clock lines, and a plurality of noncomplemented data bit lines. Each of the data clock lines and the data bit lines is a SLIO transmission line. Each SLIO transmission line is single-end terminated and preferably tapped into by way of stub resistors.Type: ApplicationFiled: June 19, 2002Publication date: July 3, 2003Applicant: Advanced Memory International, Inc.Inventors: David B. Gustavson, David V. James, Hans A. Wiggers, Peter B. Gillingham, Cormac M. O'Connell, Bruce Millar, Jean Crepeau, Kevin J. Ryan, Terry R. Lee, Brent Keeth, Troy A. Manning, Donald N. North, Desi Rhoden, Henry Stracovsky, Yoshikazu Morooka
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Patent number: 6442644Abstract: A SLDRAM System is provided with a plurality of in-circuit, calibratable memory modules and a memory controller for issuing unicast and multicast command packets to the memory modules. Command packets are transmitted over a unidirectional command link that includes a complementary pair of command clock lines, a command FLAG line and a plurality of noncomplemented command bit lines. Each of the command clock lines, command bit lines and the FLAG line is a SLIO transmission line. Data transfer operations are carried out in response to the command packets over one or more bidirectional data links that each includes two complementary pairs of data clock lines, and a plurality of noncomplemented data bit lines. Each of the data clock lines and the data bit lines is a SLIO transmission line. Each SLIO transmission line is single-end terminated and preferably tapped into by way of stub resistors.Type: GrantFiled: August 10, 1998Date of Patent: August 27, 2002Assignee: Advanced Memory International, Inc.Inventors: David B. Gustavson, David V. James, Hans A. Wiggers, Peter B. Gillingham, Cormac M. O'Connell, Bruce Millar, Jean Crepeau, Kevin J. Ryan, Terry R. Lee, Brent Keeth, Troy A. Manning, Donald N. North, Desi Rhoden, Henry Stracovsky, Yoshikazu Morooka
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Patent number: 6434688Abstract: The present invention provides a low-cost computer system which includes a single sharable block of memory that can be independently accessible as graphics memory or main store system memory without performance degradation. Because the “appetite” for main system memory (unlike that of a display memory) is difficult to satisfy, the memory can be addressed by reallocating an unused portion of a display memory for system memory use. Reallocation of the unused display memory alleviates any need to oversize the display memory, yet realizes the cost effectiveness of using readily available memory sizes. Further, reallocation of the graphics memory avoids any need to separately consider both the system memory and the display memory in accommodating worst case operational requirements. In accordance with additional embodiments, improved efficiency of operation can be achieved to enhance concurrency between plural banks of memory when expansion memory is included.Type: GrantFiled: September 20, 1995Date of Patent: August 13, 2002Assignee: Koninklijke Philips Electronics N.V.Inventors: William Desi Rhoden, Rajeev Jayavant
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Patent number: 6377581Abstract: An optimized CPU-memory high bandwidth multibus structure simultaneously supporting design reusable blocks. A system in accordance with the present invention communicatively couples the internal components (e.g., CPU, memory, etc.) and peripheral devices (e.g., display, keyboard, etc.) of a computer system by dividing the components into two logical subdivisions. One subdivision includes the memory and CPU(s) of the computer system while the other subdivision includes the remaining components. In accordance with the present invention, each subdivision of components is interconnected to the other components of its subdivision by a bus scheme. Both subdivision bus schemes are interconnected by circuitry referred to as a bridge, which enables them to intercommunicate. As such, the components connected to the separate subdivision bus schemes are able to intercommunicate.Type: GrantFiled: May 14, 1998Date of Patent: April 23, 2002Assignee: VLSI Technology, Inc.Inventors: Vishal Anand, Desi Rhoden
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Patent number: 6008823Abstract: The present invention is directed to providing an organized memory which is accessed by multiple memory controllers while still exploiting the efficiencies which the organized memory was intended to provide. In accordance with exemplary embodiments, optimal efficiency in using the shared memory is achieved by buffering memory accesses which will not increase overhead during a memory write cycle. As a result, interruptions by one controller while another controller is accessing the shared memory are reduced to a minimum.Type: GrantFiled: August 1, 1995Date of Patent: December 28, 1999Inventors: Desi Rhoden, Judson Alan Lehman, Mike Nakahara