Patents by Inventor Diane C. Boyd
Diane C. Boyd has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6982196Abstract: A structure and method are provided in which a stress present in a film is reduced in magnitude by oxidizing the film through atomic oxygen supplied to a surface of the film. In an embodiment, a mask is used to selectively block portions of the film so that the stress is relaxed only in areas exposed to the oxidation process. A structure and method are further provided in which a film having a stress is formed over source and drain regions of an NFET and a PFET. The stress present in the film over the source and drain regions of either the NFET or the PFET is then relaxed by oxidizing the film through exposure to atomic oxygen to provide enhanced mobility in at least one of the NFET or the PFET while maintaining desirable mobility in the other of the NFET and PFET.Type: GrantFiled: November 4, 2003Date of Patent: January 3, 2006Assignee: International Business Machines CorporationInventors: Michael P. Belyansky, Diane C. Boyd, Bruce B. Doris, Oleg Gluschenkov
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Patent number: 6916698Abstract: High performance (surface channel) CMOS devices with a mid-gap work function metal gate are disclosed wherein an epitaxial layer is used for a threshold voltage Vt adjust/decrease for the PFET area, for large Vt reductions (˜500 mV), as are required by CMOS devices with a mid-gap metal gate. The present invention provides counter doping using an in situ B doped epitaxial layer or a B and C co-doped epitaxial layer, wherein the C co-doping provides an additional degree of freedom to reduce the diffusion of B (also during subsequent activation thermal cycles) to maintain a shallow B profile, which is critical to provide a surface channel CMOS device with a mid-gap metal gate while maintaining good short channel effects. The B diffusion profiles are satisfactorily shallow, sharp and have a high B concentration for devices with mid-gap metal gates, to provide and maintain a thin, highly doped B layer under the gate oxide.Type: GrantFiled: March 8, 2004Date of Patent: July 12, 2005Assignee: International Business Machines CorporationInventors: Anda C. Mocuta, Meikei Ieong, Ricky S. Amos, Diane C. Boyd, Dan M. Mocuta, Huajie Chen
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Patent number: 6911383Abstract: The present invention provides an integrated semiconductor circuit containing a planar single gated FET and a FinFET located on the same SOI substrate. Specifically, the integrated semiconductor circuit includes a FinFET and a planar single gated FET located atop a buried insulating layer of an silicon-on-insulator substrate, the planar single gated FET is located on a surface of a patterned top semiconductor layer of the silicon-on-insulator substrate and the FinFET has a vertical channel that is perpendicular to the planar single gated FET. A method of forming a method such an integrated circuit is also provided. In the method, resist imaging and a patterned hard mask are used in trimming the width of the FinFET active device region and subsequent resist imaging and etching are used in thinning the thickness of the FET device area. The trimmed active FinFET device region is formed such that it lies perpendicular to the thinned planar single gated FET device region.Type: GrantFiled: June 26, 2003Date of Patent: June 28, 2005Assignee: International Business Machines CorporationInventors: Bruce B. Doris, Diane C. Boyd, Meikei Ieong, Thomas S. Kanarsky, Jakub T. Kedzierski, Min Yang
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Patent number: 6846734Abstract: Methods of forming complementary metal oxide semiconductor (CMOS) devices having multiple-threshold voltages which are easily tunable are provided. Total salicidation with a metal bilayer (representative of the first method of the present invention) or metal alloy (representative of the second method of the present invention) is provided. CMOS devices having multiple-threshold voltages provided by the present methods are also described.Type: GrantFiled: November 20, 2002Date of Patent: January 25, 2005Assignee: International Business Machines CorporationInventors: Ricky Amos, Katayun Barmak, Diane C. Boyd, Cyril Cabral, Jr., Meikei Leong, Thomas S. Kanarsky, Jakub Tadeusz Kedzierski
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Patent number: 6841831Abstract: A sub-0.05 ?m channel length fully-depleted SOI MOSFET device having low source and drain resistance and minimal overlap capacitance and a method of fabricating the same are provided. The sub-0.05 ?m channel length fully-depleted SOI MOSFET device includes an SOI structure which contains at least an SOI layer having a channel region of a first thickness and abutting source/drain regions of a second thickness present therein, wherein the second thickness is greater than the first thickness and the source/drain regions having a salicide layer present thereon. A gate region is present also atop the SOI layer.Type: GrantFiled: June 13, 2003Date of Patent: January 11, 2005Assignee: International Business Machines CorporationInventors: Hussein I. Hanafi, Diane C. Boyd, Kevin K. Chan, Wesley Natzle, Leathen Shi
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Publication number: 20040266076Abstract: The present invention provides an integrated semiconductor circuit containing a planar single gated FET and a FinFET located on the same SOI substrate. Specifically, the integrated semiconductor circuit includes a FinFET and a planar single gated FET located atop a buried insulating layer of an silicon-on-insulator substrate, the planar single gated FET is located on a surface of a patterned top semiconductor layer of the silicon-on-insulator substrate and the FinFET has a vertical channel that is perpendicular to the planar single gated FET. A method of forming a method such an integrated circuit is also provided. In the method, resist imaging and a patterned hard mask are used in trimming the width of the FinFET active device region and subsequent resist imaging and etching are used in thinning the thickness of the FET device area. The trimmed active FinFET device region is formed such that it lies perpendicular to the thinned planar single gated FET device region.Type: ApplicationFiled: June 26, 2003Publication date: December 30, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bruce B. Doris, Diane C. Boyd, Meikei Ieong, Thomas S. Kanarsky, Jakub T. Kedzierski, Min Yang
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Patent number: 6835633Abstract: A method of fabricating a SOI wafer having a gate-quality, thin buried oxide region is provided. The wafer is fabricating by forming a substantially uniform thermal oxide on a surface of a Si-containing layer of a SOI substrate which includes a buried oxide region positioned between the Si-containing layer and a Si-containing substrate layer. Next, a cleaning process is employed to form a hydrophilic surface on the thermal oxide. A carrier wafer having a hydrophilic surface is provided and positioned near the substrate such that the hydrophilic surfaces adjoin each other. Room temperature bonding is then employed to bond the carrier wafer to the substrate. An annealing step is performed and thereafter, the Si-containing substrate of the silicon-on-insulator substrate and the buried oxide region are selectively removed to expose the Si-containing layer.Type: GrantFiled: July 24, 2002Date of Patent: December 28, 2004Assignee: International Business Machines CorporationInventors: Diane C. Boyd, Hussein I. Hanafi, Erin C. Jones, Dominic J. Schepis, Leathen Shi
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Publication number: 20040171205Abstract: High performance (surface channel) CMOS devices with a mid-gap work function metal gate are disclosed wherein an epitaxial layer is used for a threshold voltage Vt adjust/decrease for the PFET area, for large Vt reductions (˜500 mV), as are required by CMOS devices with a mid-gap metal gate. The present invention provides counter doping using an in situ B doped epitaxial layer or a B and C co-doped epitaxial layer, wherein the C co-doping provides an additional degree of freedom to reduce the diffusion of B (also during subsequent activation thermal cycles) to maintain a shallow B profile, which is critical to provide a surface channel CMOS device with a mid-gap metal gate while maintaining good short channel effects. The B diffusion profiles are satisfactorily shallow, sharp and have a high B concentration for devices with mid-gap metal gates, to provide and maintain a thin, highly doped B layer under the gate oxide.Type: ApplicationFiled: March 8, 2004Publication date: September 2, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anda C. Mocuta, Meikei Ieong, Ricky S. Amos, Diane C. Boyd, Dan M. Mocuta, Huajie Chen
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Patent number: 6762469Abstract: High performance (surface channel) CMOS devices with a mid-gap work function metal gate are disclosed wherein an epitaxial layer is used for a threshold voltage Vt adjust/decrease for the PFET area, for large Vt reductions (˜500 mV), as are required by CMOS devices with a mid-gap metal gate. The present invention provides counter doping using an in situ B doped epitaxial layer or a B and C co-doped epitaxial layer, wherein the C co-doping provides an additional degree of freedom to reduce the diffusion of B (also during subsequent activation thermal cycles) to maintain a shallow B profile, which is critical to provide a surface channel CMOS device with a mid-gap metal gate while maintaining good short channel effects. The B diffusion profiles are satisfactorily shallow, sharp and have a high B concentration for devices with mid-gap metal gates, to provide and maintain a thin, highly doped B layer under the gate oxide.Type: GrantFiled: April 19, 2002Date of Patent: July 13, 2004Assignee: International Business Machines CorporationInventors: Anda C. Mocuta, Meikei Ieong, Ricky S. Amos, Diane C. Boyd, Dan M. Mocuta, Huajie Chen
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Publication number: 20040094804Abstract: Methods of forming complementary metal oxide semiconductor (CMOS) devices having multiple-threshold voltages which are easily tunable are provided. Total salicidation with a metal bilayer (representative of the first method of the present invention) or metal alloy (representative of the second method of the present invention) is provided. CMOS devices having multiple-threshold voltages provided by the present methods are also described.Type: ApplicationFiled: November 20, 2002Publication date: May 20, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ricky Amos, Katayun Barmak, Diane C. Boyd, Cyril Cabral, Meikei Leong, Thomas S. Kanarsky, Jakub Tadeusz Kedzierski
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Publication number: 20040018699Abstract: A method of fabricating a SOI wafer having a gate-quality, thin buried oxide region is provided. The wafer is fabricating by forming a substantially uniform thermal oxide on a surface of a Si-containing layer of a SOI substrate which includes a buried oxide region positioned between the Si-containing layer and a Si-containing substrate layer. Next, a cleaning process is employed to form a hydrophilic surface on the thermal oxide. A carrier wafer having a hydrophilic surface is provided and positioned near the substrate such that the hydrophilic surfaces adjoin each other. Room temperature bonding is then employed to bond the carrier wafer to the substrate. An annealing step is performed and thereafter, the Si-containing substrate of the silicon-on-insulator substrate and the buried oxide region are selectively removed to expose the Si-containing layer.Type: ApplicationFiled: July 24, 2002Publication date: January 29, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Diane C. Boyd, Hussein I. Hanafi, Erin C. Jones, Dominic J. Schepis, Leathen Shi
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Patent number: 6660598Abstract: A sub-0.05 &mgr;m channel length fully-depleted SOI MOSFET device having low source and drain resistance and minimal overlap capacitance and a method of fabricating the same are provided. In accordance with the method of the present invention, at least one dummy gate region is first formed atop an SOI layer. The dummy gate region includes at least a sacrificial polysilicon region and first nitride spacers located on sidewalls of the sacrificial polysilicon region. Next, an oxide layer that is coplanar with an upper surface of the dummy gate region is formed and then the sacrificial polysilicon region is removed to expose a portion of the SOI layer. A thinned device channel region is formed in the exposed portion of the SOI layer and thereafter inner nitride spacers are formed on exposed walls of the fist nitride spacers. Next, a gate region is formed over the thinned device channel region and then the oxide layer is removed so as to expose thicker portions of the SOI layer than de device channel region.Type: GrantFiled: February 26, 2002Date of Patent: December 9, 2003Assignee: International Business Machines CorporationInventors: Hussein I. Hanafi, Diane C. Boyd, Kevin K. Chan, Wesley Natzle, Leathen Shi
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Publication number: 20030211681Abstract: A sub-0.05 &mgr;m channel length fully-depleted SOI MOSFET device having low surface and drain resistance and minimal overlap capacitance and a method of fabricating the same are provided. The sub-0.05 &mgr;m channel length fully-depleted SOI MOSFET device includes an SOI structure which contains at least an SOI layer having a channel region of a first thickness and abutting source/drain regions of a second thickness present therein, wherein the second thickness is greater than the first thickness and the source/drain regions having a salicide layer present thereon. A gate region is present also atop the SOI layer.Type: ApplicationFiled: June 13, 2003Publication date: November 13, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hussein I. Hanafi, Diane C. Boyd, Kevin K. Chan, Wesley Natzle, Leathen Shi
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Publication number: 20030197230Abstract: High performance (surface channel) CMOS devices with a mid-gap work function metal gate are disclosed wherein an epitaxial layer is used for a threshold voltage Vt adjust/decrease for the PFET area, for large Vt reductions (˜500 mV), as are required by CMOS devices with a mid-gap metal gate. The present invention provides counter doping using an in situ B doped epitaxial layer or a B and C co-doped epitaxial layer, wherein the C co-doping provides an additional degree of freedom to reduce the diffusion of B (also during subsequent activation thermal cycles) to maintain a shallow B profile, which is critical to provide a surface channel CMOS device with a mid-gap metal gate while maintaining good short channel effects. The B diffusion profiles are satisfactorily shallow, sharp and have a high B concentration for devices with mid-gap metal gates, to provide and maintain a thin, highly doped B layer under the gate oxide.Type: ApplicationFiled: April 19, 2002Publication date: October 23, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anda C. Mocuta, Meikei Ieong, Ricky S. Amos, Diane C. Boyd, Dan M. Mocuta, Huajie Chen
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METHOD OF FORMING A FULLY-DEPLETED SOI (SILICON-ON-INSULATOR) MOSFET HAVING A THINNED CHANNEL REGION
Publication number: 20030162358Abstract: A sub-0.05 &mgr;m channel length fully-depleted SOI MOSFET device having low source and drain resistance and minimal overlap capacitance and a method of fabricating the same are provided. The sub-0.05 &mgr;m channel length fully-depleted SOI MOSFET device includes an SOI structure which contains at least an SOI layer having a channel region of a first thickness and abutting source/drain regions of a second thickness present therein, wherein the second thickness is greater than the first thickness and the source/drain regions having a salicide layer present thereon. A gate region is present also atop the SOI layer.Type: ApplicationFiled: February 26, 2002Publication date: August 28, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hussein I. Hanafi, Diane C. Boyd, Kevin K. Chan, Wesley Natzle, Leathen Shi -
Patent number: 6593617Abstract: Metal oxide semiconductor field effect transistor (MOSFET) comprising a drain region and source region which enclose a channel region. A thin gate oxide is situated on the channel region and a gate conductor with vertical side walls is located on this gate oxide. The interfaces between the source region and channel region and the drain region and channel region are abrupt.Type: GrantFiled: February 19, 1998Date of Patent: July 15, 2003Assignee: International Business Machines CorporationInventors: Diane C. Boyd, Stuart M. Burns, Hussein I. Hanafi, Yuan Taur, William C. Wille
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Patent number: 6461529Abstract: A process and etchant gas composition for anisotropically etching a trench in a silicon nitride layer of a multilayer structure. The etchant gas composition has an etchant gas including a polymerizing agent, a hydrogen source, an oxidant, and a noble gas diluent. The oxidant preferably includes a carbon-containing oxidant component and an oxidant-noble gas component. The fluorocarbon gas is selected from CF4, C2F6, and C3F8; the hydrogen source is selected from CHF3, CH2F2, CH3F, and H2; the oxidant is selected from CO, CO2, and O2; and the noble gas diluent is selected from He, Ar, and Ne. The constituents are added in amounts to achieve an etchant gas having a high nitride selectivity to silicon oxide and photoresist. A power source, such as an RF power source, is applied to the structure to control the directionality of the high density plasma formed by exciting the etchant gas.Type: GrantFiled: April 26, 1999Date of Patent: October 8, 2002Assignee: International Business Machines CorporationInventors: Diane C. Boyd, Stuart M. Burns, Hussein I. Hanafi, Waldemar W. Kocon, William C. Wille, Richard Wise
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Patent number: 6221562Abstract: An image reversal method of turning hybrid photoresist spaces into resist lines for sub-feature size applications. The sub-feature size space width of the high resolution hybrid photoresist is largely independent of the lithographic process and mask reticles. These sub-feature size spaces formed by the hybrid resist are then turned into sub-feature size lines using Spin-On-Glass, SOG. The SOG is first coated over the entire patterned hybrid resist to fill in the hybrid spaces and cover the photoresist. SOG is then recessed back to expose the photoresist layer. The exposed photoresist is then removed. The sub-feature size lines are then left behind as a mask to pattern the same onto the underlying films on the substrate.Type: GrantFiled: November 13, 1998Date of Patent: April 24, 2001Assignee: International Business Machines CorporationInventors: Diane C. Boyd, Toshiharu Furukawa, Steven J. Holmes, William H. Ma, Paul A. Rabidoux, David V. Horak
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Patent number: 6143635Abstract: Metal oxide semiconductor field effect transistor (MOSFET) including a drain region and a source region adjacent to a channel region. A gate oxide is situated on the channel region and a gate conductor with vertical side walls is placed on the gate oxide. The MOSFET further includes a threshold adjust implant region and/or punch through implant region being aligned with respect to the gate conductor and limited to an area underneath the gate conductor.Type: GrantFiled: August 16, 1999Date of Patent: November 7, 2000Assignee: International Business Machines CorporationInventors: Diane C. Boyd, Stuart M. Burns, Hussein I. Hanafi, Yuan Taur, William C. Wille
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Patent number: 6040214Abstract: A method for the formation of field effect transistors (FETs), and more particularly metal oxide field effect transistors (MOSFETs), comprising the steps of: forming a dielectric stack on a semiconductor structure; defining an etch window on the dielectric stack; defining a gate hole in the dielectric stack by transferring the etch window into the dielectric stack using a reactive ion etching (RIE) process; depositing a side wall layer; removing the side wall layer from horizontal surfaces of the dielectric stack and gate hole such that side wall spacers remain which reduce the lateral size of the gate hole; depositing a gate conductor such that it fills the gate hole; removing the gate conductor covering the portions of the semiconductor structure surrounding the gate hole; removing at least part of the dielectric stack; and removing the side wall spacers.Type: GrantFiled: February 19, 1998Date of Patent: March 21, 2000Assignee: International Business Machines CorporationInventors: Diane C. Boyd, Stuart M. Burns, Hussein I. Hanafi, Yuan Taur, William C. Wille