Abstract: The present invention relates to the field of embedded processing systems and electronic control units (ECUs)and to autonomic embedded computing solutions. The present invention proposes to remove or extract the application-specific support functions and respective I/O subsystems from the main processors or controllers of the system, to include said extracted circuits into a respective number of ASIC chips or the like, and to connect them preferably via a supervising General Controller Unit (12) to a plurality of standard and low-price processors (40), which have the task to supply the ASIC and the multiple functions thereof with enough computing power.

Abstract: Switching method and apparatus for assigning a communication grant to a first processing unit in a communication network comprising a plurality of processing units, each processing unit being connected to each other processing unit of the plurality of processing units. The switching method includes steps of performing an identical arbitration procedure for a communication grant by each of the plurality of processing units, and switching at least one of the plurality of processing units according to the identical arbitration procedure.

Abstract: The invention relates to a method of routing a message in a network in which processing units have virtual addresses based on a spatial coordinate system. When a message including a target address is received at a processing unit, the target address is compared to the address of the receiving unit. If the addresses match, the message is processed by the receiving unit. If the addresses don't match, the first unit identifies nearest neighboring unit to which the message can be forwarded. The process is repeated until the message reaches the target system.

Abstract: A Dynamic Storage Subsystem Morphing (DSSM) mechanism (40) is connected to a plurality of storage subsystem resources, which reserve some storage area each non-donor ECU (12), ready for a “slot-down/up” access by a respective non-donor ECU having a storage subsystem (24) breakdown. The slot-down process enables the use of a high physical address range by the non-donor processor provided with addressing capabilities sufficient only for addressing lower ranges.

Abstract: In a processor system 1 for audio processing, such as voice recognition and text-to-speech, a dedicated front-end processor, a core processor and a dedicated back-end processor are provided which are coupled by dual access stack. When an analog audio signal is inputted core processor is invoked only when a certain amount of data is present in the dual access stack. Likewise the back-end processor is invoked only when a certain amount of data is present in the dual access stack. This way the overall processing power required by the processing task is minimised as well as the power consumption of the processor system.

Abstract: A processor unit for a data-processing-aided electronic control system in a motor vehicle, in which the processor unit operates in real-time and contains within its functional structure a scalable computing unit and a vehicle interface unit, as well as (preferably) a communication coprocessor as separate structural components.

Abstract: A processor unit for a data-processing-aided electronic control system in a motor vehicle, in which the processor unit operates in real-time and contains within its functional structure a scalable computing unit and a vehicle interface unit, as well as (preferably) a communication coprocessor as separate structural components.

Abstract: This discloses a pattern generator having a programmable product cycle timer in which a pulse train, i.e., the pattern generated can be repeated or switched from a first pulse frequency to a second pulse frequency without the usual transient switching periods between pulses. The invention accomplishes this by providing the generator with a cycle timer using a clock operating in conjunction with a down counter so that at a pre-selected time interval, before the end of the pulse is achieved, a test is made to determine if a required condition needing a different pulse frequency exists. If such a condition does not exist the present pulse frequency is reinitiated so that at count 0 it is repeated without delay. If the required condition does exist loading of the needed pulse frequency is initiated so that upon termination of the presently existing pulse at count 0, the newly selected pulse will be introduced into the product being tested without delay.