Abstract: Electronic devices having image-based data input systems are described. In one aspect, an electronic device includes a window, multiple indicia, an image sensor, and a data input processor. The window has a contact surface with an input region. The multiple indicia are viewable in the input region of the contact surface. The image sensor is constructed and arranged to produce image signals corresponding to images of the input region. The data input processor is coupled to the image sensor and is operable to produce input signals based on image signals produced by the image sensor and a mapping between areas of the input region images and locations of the input indicia.

Abstract: An image sensor. The image sensor array includes a substrate. An interconnect structure is formed adjacent to the substrate. An amorphous silicon electrode layer is adjacent to the interconnect structure. The amorphous silicon electrode layer includes electrode ion implantation regions between pixel electrode regions. The pixel electrode regions define cathodes of an array of image sensors. The electrode ion implantation regions provide physical isolation between the pixel electrode regions. The cathodes are electrically connected to the interconnect structure. An amorphous silicon I-layer is adjacent to the amorphous silicon electrode layer. The amorphous silicon I-layer forms an inner layer of each of the image sensors. A transparent electrode layer is formed adjacent to the image sensors. An inner surface of the transparent electrode is electrically connected to anodes of the image sensors and the interconnect structure.

Abstract: An image sensor and method of manufacture therefor includes a substrate having pixel control circuitry. Dielectric layers on the substrate include interconnects in contact with the pixel control circuitry and with pixel electrodes. An intrinsic layer is over the pixel electrodes and has a gap provided between the pixel electrodes. An intrinsic-layer covering layer is over the intrinsic layer and a transparent contact layer over the intrinsic-layer covering and the interconnects. The intrinsic, intrinsic-layer covering, and transparent contact layer interact in different combinations to provide a pixel isolation system for the image sensor.

Abstract: A method of fabricating nanosized holes with controlled geometries employs tools and methods developed in the microelectronics industry. The method exploits the fact that epitaxially grown film thicknesses can be controlled within a few atomic monolayers and that by using etching techniques, trenches and channels can be created that are only a few nanometers wide. The method involves bonding two shallow channels at an angle such that a nanopore is defined by the intersection. Thus, a nanopore-defining device includes a nanopore with dimensions that are determined by the dimensions and orientations of the intersecting channels, with the dimensions being accurately controlled within a few monolayers.

Abstract: Devices are disclosed having one or more detection sites. The devices comprise a conductive layer and a plurality of separate conductive elements. The conductive layer has a plurality of openings therethrough and is at equipotential. Each of the conductive elements is exposed within a respective opening in the conductive layer and is separated therefrom by an insulating material to provide an exposed surface of the insulating material thereby providing detection sites. The detection sites or groups thereof are electrically isolated from one another. The electrical properties of the exposed surfaces are individually electrically addressable and readable by virtue of the conductive elements and the conductive layer. The exposed surface usually has a reactant attached thereto. The reactant may be the same at each detection site or the reactant at one site may be different from a reactant at another site.

Abstract: A two-color photo-detector capable of sensing two colors at a single photo-detector location is provided having a lower photo-detector element resident in the bulk silicon and an upper photo-detector element elevated above the lower photo-detector element. The color sensitivity of each of the photo-detector elements is determined according to the absorption curve of the upper photo-detector element, the thickness of the upper photo-detector element and the color filter array, if any. The elevated upper photo-detector element overlies the circuitry needed for both the upper photo-detector element and the lower photo-detector element. In order to accurately sample color within an array of two-color photo-detectors without a color filter array, two different thicknesses for the upper photo-detector elements of adjacent two-color photo-detectors are used. Therefore, each pair of two-color photo-detectors within the array senses four different colors (i.e.

Abstract: A digital image system is disclosed having a sensor with an elevated two-color photo-detector for sensing two different color values in combination with a single-color photo-detector for sensing a third color value. Minimal demosaicing is performed to obtain at least one luminance value at each photo-detector location. The sampled chrominance values and sampled and demosaiced luminance values are directly compressed without converting between color spaces and with minimal or no processing required. With a reduced amount of image processing prior to image compression, all of the pre-compression image processing may be performed on the image sensor itself instead of on a separate image processing system.

Abstract: An array of image sensors that includes ion implantation regions that provide physical isolation between the pixel electrode regions. The physical isolation reduces coupling and cross-talk between the image sensors. The array of isolated image sensors can be formed by a simple fabrication process.

Abstract: A method of fabricating nanosized holes with controlled geometries employs tools and methods developed in the microelectronics industry. The method exploits the fact that epitaxially grown film thicknesses can be controlled within a few atomic monolayers and that by using etching techniques, trenches and channels can be created that are only a few nanometers wide. The method involves bonding two shallow channels at an angle such that a nanopore is defined by the intersection. Thus, a nanopore-defining device includes a nanopore with dimensions that are determined by the dimensions and orientations of the intersecting channels, with the dimensions being accurately controlled within a few monolayers.

Abstract: An image sensor and method of manufacture therefor includes a substrate having pixel control circuitry. Dielectric layers on the substrate include interconnects in contact with the pixel control circuitry and with pixel electrodes. An intrinsic layer is over the pixel electrodes and has a gap provided between the pixel electrodes. An intrinsic-layer covering layer is over the intrinsic layer and a transparent contact layer over the intrinsic-layer covering and the interconnects. The intrinsic, intrinsic-layer covering, and transparent contact layer interact in different combinations to provide a pixel isolation system for the image sensor.

Abstract: An image sensor. The image sensor array includes a substrate. An interconnect structure is formed adjacent to the substrate. An amorphous silicon electrode layer is adjacent to the interconnect structure. The amorphous silicon electrode layer includes electrode ion implantation regions between pixel electrode regions. The pixel electrode regions define cathodes of an array of image sensors. The electrode ion implantation regions provide physical isolation between the pixel electrode regions. The cathodes are electrically connected to the interconnect structure. An amorphous silicon I-layer is adjacent to the amorphous silicon electrode layer. The amorphous silicon I-layer forms an inner layer of each of the image sensors. A transparent electrode layer is formed adjacent to the image sensors. An inner surface of the transparent electrode is electrically connected to anodes of the image sensors and the interconnect structure.

Abstract: A digital color image sensor is disclosed having an elevated two-color photo-detector in combination with a single-color photo-detector. At least part of the circuitry associated with the two-color photo-detector may be integrated under the single-color photo-detector, which results in a smaller and less expensive photo-detector for a color image sensor. In addition, the two-color photo-detector photo-detectors are electrically isolated from each other, thereby improving the dynamic range of each photo-detector. The isolation is achieved by implementing one of the photo-detectors of the two-color photo-detector within the bulk silicon and elevating the other photo-detector of the two-color photo-detector above the bulk silicon.

Abstract: An array of light-sensitive sensors utilizes bipolar phototransistors that are formed of multiple amorphous semiconductor layers, such as silicon. In the preferred embodiment, the bipolar transistors are open base devices. In this preferred embodiment, the holes that are generated by reception of incoming photons to a particular open base phototransistor provide current injection to the base region of the phototransistor. The collector region is preferably an intrinsic amorphous silicon layer. The phototransistors may be operated in either an integrating mode in which bipolar current is integrated or a static mode in which a light-responsive voltage is monitored.

Abstract: A fabrication method for providing isolation between adjacent regions of an integrated circuit includes providing a guard layer over field edges that are the interfaces between field oxide regions and diffusion regions in which dopant is introduced. The guard layer will inhibit introduction of dopant along the field-edge, so that a substantially dopant-free transition strip is formed. The transition strip inhibits current leakage from the active region to the field oxide region. In one embodiment, the active region is an active area diode, such as used to form an Active Pixel Sensor (APS) pixel. The guard layer is biased so as to further inhibit current leakage during circuit operation. In another embodiment, the method is used in the fabrication of transistors for APS pixels having an overlay photodiode structure.

Abstract: A fabrication method for providing isolation between adjacent regions of an integrated circuit includes providing a guard layer over field edges that are the interfaces between field oxide regions and diffusion regions in which dopant is introduced. The guard layer will inhibit introduction of dopant along the field-edge, so that a substantially dopant-free transition strip is formed. The transition strip inhibits current leakage from the active region to the field oxide region. In one embodiment, the active region is an active area diode, such as used to form an Active Pixel Sensor (APS) pixel. The guard layer is biased so as to further inhibit current leakage during circuit operation. In another embodiment, the method is used in the fabrication of transistors for APS pixels having an overlay photodiode structure.

Abstract: A structure and a method for providing structural stability at an interface between two poorly adhering layers in a semiconductor device involve providing anchoring channels in one of the poorly adhering layers through which the other poorly adhering layer can be anchored to a third layer. Specifically, the structure and method are applicable to a three-layer stack having a top layer of amorphous silicon, a middle layer of titanium nitride, and a bottom layer of oxide. In order to reduce susceptibility to delamination between the amorphous silicon layer and the titanium nitride layer, the anchoring channels are created in the titanium nitride layer to allow the amorphous silicon to attach to the oxide layer. Because the amorphous silicon layer and the oxide layer exhibit good adhesion between each other, delamination between the amorphous silicon layer and the titanium nitride layer is minimized.

Abstract: A fabrication method for providing isolation between adjacent regions of an integrated circuit includes providing a guard layer over field edges that are the interfaces between field oxide regions and diffusion regions in which dopant is introduced. The guard layer will inhibit introduction of dopant along the field-edge, so that a substantially dopant-free transition strip is formed. The transition strip inhibits current leakage from the active region to the field oxide region. In one embodiment, the active region is an active area diode, such as used to form an Active Pixel Sensor (APS) pixel. The guard layer is biased so as to further inhibit current leakage during circuit operation. In another embodiment, the method is used in the fabrication of transistors for APS pixels having an overlay photodiode structure.

Abstract: A fabrication method for providing isolation between adjacent regions of an integrated circuit includes providing a guard layer over field edges that are the interfaces between field oxide regions and diffusion regions in which dopant is introduced. The guard layer will inhibit introduction of dopant along the field-edge, so that a substantially dopant-free transition strip is formed. The transition strip inhibits current leakage from the active region to the field oxide region. In one embodiment, the active region is an active area diode, such as used to form an Active Pixel Sensor (APS) pixel. The guard layer is biased so as to further inhibit current leakage during circuit operation. In another embodiment, the method is used in the fabrication of transistors for APS pixels having an overlay photodiode structure.

Abstract: A fabrication method for providing isolation between adjacent regions of an integrated circuit includes providing a guard layer over field edges that are the interfaces between field oxide regions and diffusion regions in which dopant is introduced. The guard layer will inhibit introduction of dopant along the field-edge, so that a substantially dopant-free transition strip is formed. The transition strip inhibits current leakage from the active region to the field oxide region. In one embodiment, the active region is an active area diode, such as used to form an Active Pixel Sensor (APS) pixel. The guard layer is biased so as to further inhibit current leakage during circuit operation. In another embodiment, the method is used in the fabrication of transistors for APS pixels having an overlay photodiode structure.

Abstract: A method for fabricating dual gate dielectric layers on a semiconductor substrate involves utilizing a single photolithographic step to form layer stacks having two different gate dielectric layers and associated polysilicon layers, and then utilizing a physical planarization process to remove excess polysilicon and silicon oxide. According to the method, a first gate dielectric is formed on the first and second device areas of a substrate. A first polysilicon layer is deposited onto the first gate dielectric, and portions of the first polysilicon layer are removed utilizing a photolithographic process. The first gate dielectric is removed over the second device area, and a second, thinner gate dielectric is formed over the second device area. A second polysilicon layer is formed over the second gate dielectric and over the first polysilicon layer.