Abstract: A structure and a method for providing structural stability at an interface between two poorly adhering layers in a semiconductor device involve providing anchoring channels in one of the poorly adhering layers through which the other poorly adhering layer can be anchored to a third layer. Specifically, the structure and method are applicable to a three-layer stack having a top layer of amorphous silicon, a middle layer of titanium nitride, and a bottom layer of oxide. In order to reduce susceptibility to delamination between the amorphous silicon layer and the titanium nitride layer, the anchoring channels are created in the titanium nitride layer to allow the amorphous silicon to attach to the oxide layer. Because the amorphous silicon layer and the oxide layer exhibit good adhesion between each other, delamination between the amorphous silicon layer and the titanium nitride layer is minimized.

Abstract: An array of active pixel sensors. The array of active pixel sensors includes a substrate that includes electronic circuitry. An interconnect structure is formed adjacent to the substrate. The interconnect structure includes a plurality of conductive vias. A plurality of conductive guard rings are formed adjacent to the interconnect structure. Each conductive guard ring is electrically connected to the substrate through at least one of the conductive vias. A plurality of photo diode sensors are formed adjacent to the interconnect structure. Each photo diode sensor is surrounded by at least one of the conductive guard rings. Each photo diode sensor includes a pixel electrode. The pixel electrode is electrically connected to the substrate through a corresponding conductive via. An I-layer is formed adjacent to the pixel electrode. The array of active pixel sensors further includes a transparent conductive layer formed adjacent to the photo diode sensors.

Abstract: An image pixel sensor array. The image pixel sensor array includes a substrate. An interconnect structure is formed adjacent to the substrate. A plurality of image pixel sensors are formed adjacent to the interconnect structure. Each image pixel sensor includes a pixel electrode, and an I-layer formed adjacent to the pixel electrode. The I-layer includes a first surface adjacent to the pixel electrode, and a second surface opposite the first surface. The first surface includes a first surface area which is less than a second surface area of the second surface. The image pixel sensor array further includes an insulating material between each image pixel sensor, and a transparent electrode formed over the image pixel sensors. The transparent electrode electrically connects the image pixel sensors and the interconnect structure.

Abstract: An active pixel sensor. The active pixel sensor includes a substrate, an interconnect structure adjacent to the substrate, and at least one photo sensor adjacent to the interconnect structure. At least one photo sensor is formed adjacent to the interconnect structure. Each photo sensor includes a pixel electrode which includes a patterned doped semiconductor layer. An I-layer is formed adjacent to the patterned doped semiconductor layer. A transparent electrode is formed adjacent to the I-layer. A method of forming the active pixel sensor includes forming an interconnect structure over a substrate. Next, a doped semiconductor layer is deposited over the interconnect structure. The doped semiconductor layer is etched forming pixel electrode. An I-layer is deposited over the pixel electrodes. Finally, a transparent conductive layer is deposited over the I-layer.

Abstract: A color detection active pixel sensor. The color detection active pixel sensor includes a substrate. A diode is electrically connected to a first doped region of the substrate. The diode conducts charge when the diode receives photons having a first range of wavelengths. The substrate includes a second doped region. The second doped region conducts charge when receiving photons having a second range of wavelengths. The photons having the second range of wavelengths passing through the diode substantially undetected by the diode. The substrate can include a doped well within the substrate. The doped well conducts charge when receiving photons having a third range of wavelengths. The photons having the third range of wavelengths pass through the diode substantially undetected by the diode.

Abstract: Small feature CMOS defect analysis of SRAM circuits is made less time consuming with the inclusion of an in-circuit test connection which is brought to external contact pads. External measurement and circuit forcing are accomplished via the external contact pads. A fault library for comparison to automated tests results provides faster resolution of process defects.

Abstract: An active pixel sensor. The active pixel sensor includes a substrate, an interconnect structure adjacent to the substrate, and at least one photo sensor adjacent to the interconnect structure. Each photo sensor includes an individual pixel electrode. An I-layer is formed over all of the pixel electrodes. A transparent electrode is formed over the I-layer. An inner surface of the transparent electrode is electrically connected to the I-layer and the interconnect structure.

Abstract: A dual-inlaid damascene contact having a polished surface for directly communicating an electrically conductive layer to a semiconductor layer. A dielectric layer is formed on the electrically conductive layer. A dual-inlaid cavity is formed by etching a via cavity and a contact cavity into the dielectric layer. A damascene contact is formed by depositing tungsten into the dual-inlaid cavity. Chemical-mechanical polishing is used to planarize and smooth a surface of the damascene contact until the surface is coplanar with the dielectric layer. A semiconductor layer is then deposited on the damascene contact. The semiconductor layer can be the node of an amorphous silicon P-I-N photodiode. Electrical interconnection between the node of the photodiode and the electrically conductive layer is accomplished without using an intermediate electrode, and the smooth damascene contact improves surface adhesion, reduces contact resistance, and provides a discrete connection to the semiconductor layer.

Abstract: In a bipolar device, selective epitaxial silicon provides an improved intrinsic-extrinsic base link. A trench physically separates an intrinsic and extrinsic base portion. The trench includes sidewalls having a thin oxide layer formed thereon. The bottom of the trench is exposed during processing. A shallow link between the intrinsic-extrinsic regions of a bipolar transistor base is formed by depositing a heavily boron doped layer of silicon on the exposed portion of the trench. During subsequent processing, including rapid thermal anneal, there is some boron out-diffusion which forms a shallow diffused intrinsic-extrinsic base link.

Abstract: A method of annealing a wafer in a rapid thermal annealer is disclosed. The walls of the chamber are heated more rapidly than is the wafer. In a preferred embodiment, the interior of the graphite walls of the annealer is lined with a molybdenum sheet which is open toward the lamps that heat the chamber. Thus, the walls heat very rapidly to a temperature greater than the condensation point of arsenic, preventing arsenic condensation on the walls. Effective annealing can be achieved at wall temperatures in the range of 500.degree. to 600.degree. C. Prior to the heat ramp up, an arsenic atmosphere, preferably trimethylarsenic (TMAs) at an appropriate overpressure is introduced. This overpressure is maintained both during the heating and cooling cycle. By the use of this method, the exposure time for annealing can be reduced from prior times of as much as 20 minutes to as little as 10 seconds.