Abstract: A memory system in an integrated circuit and a method of operation. The system includes multiple magnetic tunnel junction (MTJ) structures, each MTJ structure storing a logic value according to a resistive state. A selection switch device associated with a respective MTJ structure is activated to select one of the multiple MTJ structures at a time. An output circuit is configured to sense the resistive state of a selected MTJ structure, the output circuit having a selectable input reference resistance value according to a selected first reference resistance or a second reference resistance value, and outputting a first logic value of the selected MTJ structure responsive to a resistive state of the MTJ structure and a selected first resistance reference value, or alternately outputting a second logic value of the selected MTJ structure responsive to the resistive state of the MTJ structure and a selected second resistance reference value.

Abstract: A via interconnect structure for an MRAM device is provided. The via interconnect structure includes an interlayer dielectric layer having a via formed therein, a magnetic metal layer formed in the via, the magnetic metal layer having a cavity formed therein, and a nonmagnetic metal layer formed in the cavity of the magnetic metal layer. The magnetic metal layer is configured such that magnetization vectors of the magnetic metal layer are least substantially in-plane relative to an MRAM stack structure of the MRAM device.

Abstract: A replacement bottom electrode structure process is provided in which a patterned stack containing a MTJ pillar and a top electrode structure is fabricated and passivated on a sacrificial dielectric material plug that is embedded in a dielectric capping layer. The sacrificial dielectric material plug is then removed and replaced with a bottom electrode structure. The replacement bottom electrode structure process of the present application allows the MTJ patterning to be misalignment tolerate and fully eliminates the potential yield loss from the bottom electrode structure.

Abstract: Techniques and circuits for testing and configuring bias voltage or bias current for write operations in memory devices are presented. Registers and nonvolatile storage is included on the memory devices for storing values used to control testing of the memory devices as well as for configuring parameters related to both testing and normal operation.

Abstract: A memory element and methods of constructing the memory element are described. The memory element may include a bottom electrode structure having an uppermost portion of a first dimension. The memory element may further include a MTJ pillar having a bottommost portion forming an interface with the uppermost portion of the bottom electrode structure. The bottommost portion of the MTJ pillar may have a second dimension that is less than the first dimension. The memory element may further include oxidized metal particles located on an outermost sidewall of the MTJ pillar. The memory element may further include a top electrode structure located in the MTJ pillar.

Abstract: A replacement bottom electrode structure process is provided in which a patterned stack containing a MTJ pillar and a top electrode structure is fabricated and passivated on a sacrificial dielectric material plug that is embedded in a dielectric capping layer. The sacrificial dielectric material plug is then removed and replaced with a bottom electrode structure. The replacement bottom electrode structure process of the present application allows the MTJ patterning to be misalignment tolerate and fully eliminates the potential yield loss from the bottom electrode structure.

Abstract: A memory system in an integrated circuit and a method of operation. The system includes multiple magnetic tunnel junction (MTJ) structures, each MTJ structure storing a logic value according to a resistive state. A selection switch device associated with a respective MTJ structure is activated to select one of the multiple MTJ structures at a time. An output circuit is configured to sense the resistive state of a selected MTJ structure, the output circuit having a selectable input reference resistance value according to a selected first reference resistance or a second reference resistance value, and outputting a first logic value of the selected MTJ structure responsive to a resistive state of the MTJ structure and a selected first resistance reference value, or alternately outputting a second logic value of the selected MTJ structure responsive to the resistive state of the MTJ structure and a selected second resistance reference value.

Abstract: A magnetoresistive element (e.g., a spin-torque magnetoresistive memory element) includes a fixed magnetic layer, a free magnetic layer, having a high-iron alloy interface region located along a surface of the free magnetic layer, wherein the high-iron alloy interface region has at least 50% iron by atomic composition, and a first dielectric, disposed between the fixed magnetic layer and the free magnetic layer. The magnetoresistive element further includes a second dielectric, having a first surface that is in contact with the surface of the free magnetic layer, and an electrode, disposed between the second dielectric and a conductor. The electrode includes: (i) a non-ferromagnetic portion having a surface that is in contact with a second surface of the second dielectric, and (ii) a second portion having at least one ferromagnetic material disposed between the non-ferromagnetic portion of the electrode and the conductor.

Abstract: In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.

Abstract: Magnetic field assisted magnetoresistive random access memory (MRAM) structures, integrated circuits including MRAM structures, and methods for fabricating integrated circuits including MRAM structures are provided. An exemplary integrated circuit includes a magnetoresistive random access memory (MRAM) structure and a magnetic field assist structure to generate a selected net magnetic field on the MRAM structure.

Abstract: Integrated circuits and methods for fabricating integrated circuits with magnetic tunnel junction (MTJ) structures are provided. An exemplary method for fabricating an integrated circuit includes forming a magnetic tunnel junction (MTJ) structure and conformally forming a metal oxide encapsulation layer over and around the MTJ structure. The method further includes removing a portion of the metal oxide encapsulation layer over MTJ structure. Also, the method includes forming a conductive via over and in electrical communication with the top surface of the MTJ structure.

Abstract: Magnetic field assisted magnetoresistive random access memory (MRAM) structures, integrated circuits including MRAM structures, and methods for fabricating integrated circuits including MRAM structures are provided. An exemplary integrated circuit includes a magnetoresistive random access memory (MRAM) structure and a magnetic field assist structure to generate a selected net magnetic field on the MRAM structure.

Abstract: Spin transfer torque magnetic random access memory structures, integrated circuits, and methods for fabricating integrated circuits are provided. An exemplary spin transfer torque magnetic random access memory structure has a perpendicular magnetic orientation, and includes a bottom electrode and a base layer over the bottom electrode. The base layer includes a seed layer and a roughness suppression layer. The spin transfer torque magnetic random access memory structure further includes a hard layer over the base layer. Also, the spin transfer torque magnetic random access memory structure includes a magnetic tunnel junction (MTJ) element with a perpendicular orientation over the hard layer and a top electrode over the MTJ element.

Abstract: A magnetoresistive element (e.g., a spin-torque magnetoresistive memory element) includes a fixed magnetic layer, a free magnetic layer, having a high-iron alloy interface region located along a surface of the free magnetic layer, wherein the high-iron alloy interface region has at least 50% iron by atomic composition, and a first dielectric, disposed between the fixed magnetic layer and the free magnetic layer. The magnetoresistive element further includes a second dielectric, having a first surface that is in contact with the surface of the free magnetic layer, and an electrode, disposed between the second dielectric and a conductor. The electrode includes: (i) a non-ferromagnetic portion having a surface that is in contact with a second surface of the second dielectric, and (ii) a second portion having at least one ferromagnetic material disposed between the non-ferromagnetic portion of the electrode and the conductor.

Abstract: A magnetoresistive element (e.g., a spin-torque magnetoresistive memory element) includes a fixed magnetic layer, a free magnetic layer, having a high-iron alloy interface region located along a surface of the free magnetic layer, wherein the high-iron alloy interface region has at least 50% iron by atomic composition, and a first dielectric, disposed between the fixed magnetic layer and the free magnetic layer. The magnetoresistive element further includes a second dielectric, having a first surface that is in contact with the surface of the free magnetic layer, and an electrode, disposed between the second dielectric and a conductor. The electrode includes: (i) a non-ferromagnetic portion having a surface that is in contact with a second surface of the second dielectric, and (ii) a second portion having at least one ferromagnetic material disposed between the non-ferromagnetic portion of the electrode and the conductor.

Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a magnetic tunnel junction stack. The magnetic tunnel junction stack includes a seed layer, first and second pinned layers, and a coupling layer. The seed layer includes holmium. The first pinned layer overlies the seed layer, where the first pinned layer is magnetic, and the non-magnetic coupling layer overlies the first pinned layer. The second pinned layer overlies the coupling layer, where the second pinned layer is also magnetic.

Abstract: Spin transfer torque magnetic random access memory structures, integrated circuits, and methods for fabricating integrated circuits are provided. An exemplary spin transfer torque magnetic random access memory structure has a perpendicular magnetic orientation, and includes a bottom electrode, a seed layer over the bottom electrode, a hard layer over the seed layer, a magnetically continuous transition layer over the hard layer, a reference layer over the magnetically continuous transition layer, a tunnel barrier layer over the reference layer, a storage layer formed over the tunnel barrier layer, and a top electrode. The reference layer, the tunnel barrier layer, and the storage layer form a magnetic tunnel junction (MTJ) element with a perpendicular orientation.

Abstract: One illustrative integrated circuit (IC) product disclosed herein includes an MRAM cell, the MRAM cell having an outer perimeter, wherein the MRAM cell comprises a bottom electrode, a top electrode and an MTJ (Magnetic Tunnel Junction) element positioned above the bottom electrode and below the top electrode. In this example, the IC product also includes an insulating material positioned around the outer perimeter of the MRAM cell and a conductive sidewall spacer comprised of a metal-containing shielding material positioned around the outer perimeter of the MRAM cell, wherein the insulating material is positioned between the conductive sidewall spacer and the MRAM cell.

Abstract: Spin transfer torque magnetic random access memory structures, integrated circuits, and methods for fabricating integrated circuits are provided. An exemplary spin transfer torque magnetic random access memory structure has a perpendicular magnetic orientation, and includes a bottom electrode and a base layer over the bottom electrode. The base layer includes a seed layer and a roughness suppression layer. The spin transfer torque magnetic random access memory structure further includes a hard layer over the base layer. Also, the spin transfer torque magnetic random access memory structure includes a magnetic tunnel junction (MTJ) element with a perpendicular orientation over the hard layer and a top electrode over the MTJ element.

Abstract: Spin transfer torque magnetic random access memory structures, integrated circuits, and methods for fabricating integrated circuits are provided. An exemplary spin transfer torque magnetic random access memory structure has a perpendicular magnetic orientation, and includes a bottom electrode, a seed layer over the bottom electrode, a hard layer over the seed layer, a magnetically continuous transition layer over the hard layer, a reference layer over the magnetically continuous transition layer, a tunnel barrier layer over the reference layer, a storage layer formed over the tunnel barrier layer, and a top electrode. The reference layer, the tunnel barrier layer, and the storage layer form a magnetic tunnel junction (MTJ) element with a perpendicular orientation.