Abstract: A secure electronic structure including a plurality of sub-lithographic conductor features having non-repeating random shapes as a physical unclonable function (PUF) and an integrated circuit including the same are provided. Some of the conductor features of the plurality of conductor features form ohmic electrical contact to a fraction of regularly spaced array of conductors that are located above or beneath the plurality of conductor features having the non-repeating shapes, while other conductor features of the plurality of conductor features do not form ohmic electrical contact with any of the regularly spaced array of conductors. Thus, a unique signature of electrical continuity is provided which can be used as a PUF within an integrated circuit.

Abstract: A method of manufacturing a secure device having a physical unclonable function includes providing a first graphene layer, providing a second graphene layer and applying a variability enhancement to at least one of the first graphene layer and the second graphene layer such that a measurable property is different for each of the first graphene layer and the second graphene layer. The physical unclonable function is represented by at least the first and second graphene layers. In still another embodiment, a method of manufacturing a secure device having a physical unclonable function includes providing an integrated circuit comprising at least one graphene layer and including a measurement circuit in the integrated circuit that is configured to measure at least one property of the at least one graphene layer for authenticating the secure device. The at least one graphene layer represents the physical unclonable function.

Abstract: The present disclosure relates to secure devices having a physical unclonable function and methods of manufacturing such secure devices. One device includes at least one graphene layer representing a physical unclonable function and a measurement circuit for measuring at least one property of the at least one graphene layer. Another device includes at least a first graphene layer and a second graphene layer representing a physical unclonable function, where one of the graphene layers has been subjected to a variability enhancement such that a measurable property is different for each of the layers. A method includes providing a substrate for a secure device and providing at least one graphene layer on the substrate, the at least one graphene layer representing a physical unclonable function. The providing of the at least one graphene layer includes applying at least one variability enhancement to the at least one graphene layer.

Abstract: The present disclosure relates to a secure device having a physical unclonable function and methods of manufacturing such a secure device. The device includes a substrate and at least one high-k/metal gate device formed on the substrate. The at least one high-k/metal gate device represents the physical unclonable function. In some cases, the at least one high-k/metal gate device may be subjected a variability enhancement. In some cases, the secure device may include a measurement circuit for measuring a property of the at least one high-k/metal gate device.

Abstract: A method of manufacturing a secure device having a physical unclonable function includes embedding a phase change memory in the secure device, where the phase change memory includes a plurality of cells, and setting the phase change memory in a manner that results in a phase variation over the plurality of cells, wherein the phase variation is the physical unclonable function. A method for retrieving a cryptographic key from an integrated circuit, wherein the cryptographic key is stored in the integrated circuit, includes measuring a property of a phase change memory embedded in the integrated circuit, wherein the phase change memory includes a plurality of cells and the property is a function of a phase variation over the plurality of cells, deriving a signature from the property, and deriving the cryptographic key from the signature.

Abstract: A device having a physical unclonable function includes an integrated circuit and a phase change memory embedded in the integrated circuit and including a plurality of cells, where the phase change memory is set in a manner that creates a phase variation over the plurality of cells, and where the phase variation comprises the physical unclonable function. In another embodiment, a device having a physical unclonable function includes a phase change memory embedded in the device and comprising a plurality of cells, where the phase change memory is set in a manner that creates a phase variation over the plurality of cells, and where the phase variation comprises the physical unclonable function, and a measurement circuit for extracting the physical unclonable function from the phase change memory.

Abstract: Interconnect structures including a graphene cap located on exposed surfaces of a copper structure are provided. In some embodiments, the graphene cap is located only atop the uppermost surface of the copper structure, while in other embodiments the graphene cap is located along vertical sidewalls and atop the uppermost surface of the copper structure. The copper structure is located within a dielectric material.

Abstract: The present disclosure relates to an antifuse for preventing a flow of electrical current in an integrated circuit. One such antifuse includes a reactive material and a silicon region thermally coupled to the reactive material, where an electrical current to the reactive material causes the reactive material to release heat which transitions the silicon region from a high resistance state to a low resistance state. Another such antifuse includes a reactive material, at least one metal and a silicon region adjacent to the at least one metal and thermally coupled to the reactive material, where an electrical current to the reactive material causes the reactive material to release heat which transitions the silicon region from a high resistance state to a low resistance state.

Abstract: The present disclosure relates to integrated circuits having tamper detection and response devices and methods for manufacturing such integrated circuits. One integrated circuit having a tamper detection and response device includes at least one photovoltaic cell and at least one memory cell coupled to the at least one photovoltaic cell. When the at least one photovoltaic cell is exposed to radiation, the at least one photovoltaic cell generates a current that causes an alteration to a memory state of the at least one memory cell. Another integrated circuit having a tamper detection and response device includes at least one photovoltaic cell and a reactive material coupled to the at least one photovoltaic cell, wherein a current from the at least one photovoltaic cell triggers an exothermic reaction in the reactive material.

Abstract: The present disclosure relates to integrated circuits having tamper detection and response devices and methods for manufacturing such integrated circuits. One integrated circuit having a tamper detection and response device includes at least one reactive material and at least one memory cell coupled to the at least one reactive material. An exothermic reaction in the at least one reactive material causes an alteration to a memory state of the at least one memory cell. Another integrated circuit having a tamper detection and response device includes a substrate, at least one gate on the substrate, and a reactive material between a first well and a second well of the at least one gate. A reaction in the reactive material causes a short in the gate.

Abstract: A silicon nitride layer is provided on an uppermost surface of a graphene layer and then a hafnium dioxide layer is provided on an uppermost surface of the silicon nitride layer. The silicon nitride layer acts as a wetting agent for the hafnium dioxide layer and thus prevents the formation of discontinuous columns of hafnium dioxide atop the graphene layer. The silicon nitride layer and the hafnium dioxide layer, which collectively form a low EOT bilayer gate dielectric, exhibit continuous morphology atop the graphene layer.

Abstract: A secure electronic structure is provided including a via array as a physical unclonable function (PUF). Specifically, the secure electronic structure includes an array of electrical contact vias located between a lower level of a first regularly spaced array of conductors and an upper level of a second regularly spaced array of conductors. Each electrical contact via of the via array is individually addressed through the first regularly spaced array of conductors in the lower level and the second regularly spaced array of conductors in the upper level and has a resistance value. Each resistance value of each electrical contact via forms a distribution of resistance values, wherein the distribution of resistance values is random. This random distribution of the resistance values of the array of electrical contact vias can be used as a physical unclonable function in the electronic structure of the present disclosure.

Abstract: The present disclosure relates to a secure device having a physical unclonable function and methods of manufacturing such a secure device. The device includes a substrate and at least one high-k/metal gate device formed on the substrate. The at least one high-k/metal gate device represents the physical unclonable function. In some cases, the at least one high-k/metal gate device may be subjected a variability enhancement. In some cases, the secure device may include a measurement circuit for measuring a property of the at least one high-k/metal gate device.

Abstract: A secure electronic structure including a plurality of sub-lithographic conductor features having non-repeating random shapes as a physical unclonable function (PUF) and an integrated circuit including the same are provided. Some of the conductor features of the plurality of conductor features form ohmic electrical contact to a fraction of regularly spaced array of conductors that are located above or beneath the plurality of conductor features having the non-repeating shapes, while other conductor features of the plurality of conductor features do not form ohmic electrical contact with any of the regularly spaced array of conductors. Thus, a unique signature of electrical continuity is provided which can be used as a PUF within an integrated circuit.

Abstract: Systems and methods for providing information services are disclosed. A method includes passing an instance an object, invoked by a user, to a memory device at a hardware layer of a network information system, the object being hosted for a tenant of a network information service. The method further includes determining by a processing unit of the memory device that storage of the object is not authorized by the tenant based on a security map provided by the tenant and accessible by the processing unit within the hardware layer. The method further includes preventing storage of the instance in the memory device based on the result of the determining.

Abstract: Interconnect structures including a graphene cap located on exposed surfaces of a copper structure are provided. In some embodiments, the graphene cap is located only atop the uppermost surface of the copper structure, while in other embodiments the graphene cap is located along vertical sidewalls and atop the uppermost surface of the copper structure. The copper structure is located within a dielectric material.

Abstract: Methods for reliability testing include applying a stress voltage to a device under test (DUT); measuring a leakage current across the DUT; triggering measurement of optical emissions from the DUT based on the timing of the measurement of the leakage current; and correlating measurements of the leakage current with measurements of the optical emissions to determine a time and location of a defect occurrence within the DUT by locating instances of increased noise in the leakage current that correspond in time with instances of increased optical emissions.

Abstract: A lithographic structure comprising: an organic antireflective material disposed on a substrate, and a silicon antireflective material disposed on the organic antireflective material. The silicon antireflective material comprises a crosslinked polymer with a SiOx backbone, a chromophore, and a transparent organic group that is substantially transparent to 193 nm or 157 nm radiation. In combination, the organic antireflective material and the silicon antireflective material provide an antireflective material suitable for deep ultraviolet lithography. The invention is also directed to a process of making the lithographic structure.

Abstract: Interconnect structures including a graphene cap located on exposed surfaces of a copper structure are provided. In some embodiments, the graphene cap is located only atop the uppermost surface of the copper structure, while in other embodiments the graphene cap is located along vertical sidewalls and atop the uppermost surface of the copper structure. The copper structure is located within a dielectric material.

Abstract: Interconnect structures including a graphene cap located on exposed surfaces of a copper structure are provided. In some embodiments, the graphene cap is located only atop the uppermost surface of the copper structure, while in other embodiments the graphene cap is located along vertical sidewalls and atop the uppermost surface of the copper structure. The copper structure is located within a dielectric material.