Abstract: A controller includes an Error Correction Code (ECC) encoder adding a first parity to data to generate a data set, and encoding the data set to generate a first parity data set, a buffer temporarily storing the first parity data set, an ECC decoder decoding the first parity data set received from the buffer to generate a decoded data set, a first checker performing a Low Density Parity Check (LDPC) encoding on the decoded data set to generate an LDPC data set to which a second parity is added, and a second checker performing a syndrome check operation on the LDCP data set including the first and second parities.

Abstract: A memory controller includes a cache memory, a host control circuit, and a flash translation layer. The host control circuit receives a read command and a logical address from a host, reads out mapping information corresponding to the logical address from a buffer memory device, and caches the mapping information in the cache memory. The flash translation layer reads a physical address corresponding to the logical address from the mapping information cached in the cache memory.

Abstract: A backlight unit includes a central area and a peripheral area disposed outside the central area, the backlight unit includes a bottom chassis, a plurality of light sources disposed on a surface of the bottom chassis, a reflective layer disposed on the surface of the bottom chassis, where a plurality of light source insertion holes and a plurality of opening patterns are defined through the reflective layer, and a light correction material layer disposed between the bottom chassis and the reflective layer in the peripheral area, where the light source insertion holes expose the light sources, respectively, and the opening patterns are disposed in the peripheral area to expose at least a portion of the light correction material layer in a thickness direction.

Abstract: A memory system includes a nonvolatile memory device, a buffer memory device storing logical-physical address mapping information, and a memory controller controlling operations of the nonvolatile and buffer memory devices. The memory controller comprises a cache memory, a host control circuit, a flash translation section, and a flash control circuit. The host control circuit receives a read command and a read logical address from a host, reads mapping information corresponding to the read logical address from the buffer memory device, and caches the mapping information in the cache memory, the mapping information corresponding to the logical-physical address mapping information stored in the buffer memory device. The flash translation section reads a read physical address mapped to the read logical address from the mapping information. The flash control circuit reads data corresponding to the read command from the nonvolatile memory device based on the read physical address.

Abstract: An electronic device includes a memory controller having an improved operation speed. The memory controller includes a processor configured to generate commands for accessing data stored in a main memory, a scheduling circuit configured to store the commands and output the commands according to a preset criterion, and a filtering circuit configured to store information on an address of the main memory corresponding to a write command among the commands, provide a pre-completion response for the write command to the scheduling circuit upon receiving the write command, and provide the write command to the main memory.

Abstract: A controller includes an Error Correction Code (ECC) encoder adding a first parity to data to generate a data set, and encoding the data set to generate a first parity data set, a buffer temporarily storing the first parity data set, an ECC decoder decoding the first parity data set received from the buffer to generate a decoded data set, a first checker performing a Low Density Parity Check (LDPC) encoding on the decoded data set to generate an LDPC data set to which a second parity is added, and a second checker performing a syndrome check operation on the LDCP data set including the first and second parities.

Abstract: A memory system includes a memory device including a plurality of segments; a processor configured to generate a Read-Modify-Write (RMW) command on a target segment address corresponding to a target segment among the plurality of segments; a scheduler configured to receive the RMW command from the processor and schedule the RMW command; and a RMW unit configured to execute the RMW command on the memory device according to control of the scheduler, wherein the scheduler compares, when a plurality of RMW commands received from the processor are pending, target segment addresses of the plurality of RMW commands to re-order the plurality of RMW commands.

Abstract: Disclosed are light emitting modules and automobile illumination devices including the same. The light emitting module comprises a module substrate, a light emitting device on the module substrate, and a light guide structure apart from the module substrate and in plan view surrounding the light emitting device. The light emitting device comprises a first pixel and a second pixel each including a light emitting diode (LED) chip that emits light whose wavelength falls within a range of blue color or ultraviolet ray, and a wavelength conversion material on a top surface of at least one of the first and second pixels.

Abstract: Provided are a composite optical sheet and a liquid crystal display device including the same.

Abstract: A backlight unit includes a light source array including at least one light source which emits light and a circuit board on which the light source is disposed, and a first optical layer disposed on the light source array. The first optical layer includes a first layer which defines at least one concave portion in a bottom of the first layer, where the at least one concave portion is coupled to the light source, a second layer disposed on the first layer, the second layer guiding light incident from the first layer in one direction, a plurality of optical patterns disposed on one surface of the second layer, the plurality of optical patterns selectively emitting light passing through the one surface, and a reflective layer disposed on the bottom of the first layer.

Abstract: A memory system includes a memory device, a write buffer for buffering first and second host data, a chip-kill cache for caching one among first and second chip-kill parity candidates for the first and second host data, respectively, a chip-kill buffer having a smaller bandwidth and a larger capacity than the chip-kill cache; a chip-kill manager for generating a first chip-kill parity by performing an XOR operation on the first host data and the first chip-kill parity candidate, and generating a second chip-kill parity by performing an XOR operation on the second host data and the second chip-kill parity candidate, and a processor for controlling the memory device to program the first host data and the first chip-kill parity into a first open block and to program the second host data and the second chip-kill parity into a second open block.

Abstract: A backlight unit and a display device including the backlight unit are provided. A backlight unit includes a substrate, light sources disposed on one surface of the substrate, a first reflective film disposed on one surface of the substrate and including first openings, each of the first openings of the first reflective film exposing each of the light sources, and wavelength filter layers disposed above the first reflective film and disposed to correspond to the first openings, the wavelength filter layers are spaced apart from each other, and each of the wavelength filter layers covers at least one of the first openings.

Abstract: A controller, a memory system and an operating method thereof are disclosed. The controller controls a nonvolatile memory device and the nonvolatile memory includes a first memory module configured to store a plurality of pieces of map data read from the nonvolatile memory device; and a second memory module configured to cache map data having locality among map data received from the first memory module.

Abstract: There are provided a memory system and an operating method thereof. In a method for operating a memory system, the method includes generating a write request for write data; reading chunk data from a buffer memory in response to the write request; caching the chunk data in a cache memory; generating a read request for read data; and outputting a portion of the cached chunk data as the read data from the cache memory when the read data is included in the cached chunk data.

Abstract: An optical member includes a light guide plate, a wavelength conversion layer, and a reflective tape. The wavelength conversion layer is disposed on an upper surface of the light guide plate. The reflective tape includes a first side portion covering first side surfaces of the light guide plate and the wavelength conversion layer. The reflective tape includes a first surface and a second surface. The first surface is configured to reflect light of a first wavelength band and light of a second wavelength band different from the first wavelength band. The second surface is configured to absorb the light of the first wavelength band.

Abstract: A controller includes an Error Correction Code (ECC) encoder adding a first parity to data to generate a data set, and encoding the data set to generate a first parity data set, a buffer temporarily storing the first parity data set, an ECC decoder decoding the first parity data set received from the buffer to generate a decoded data set, a first checker performing a Low Density Parity Check (LDPC) encoding on the decoded data set to generate an LDPC data set to which a second parity is added, and a second checker performing a syndrome check operation on the LDCP data set including the first and second parities.

Abstract: There are provided a memory system and an operating method thereof. In a method for operating a memory system, the method includes generating a write request for write data; reading chunk data from a buffer memory in response to the write request; caching the chunk data in a cache memory; generating a read request for read data; and outputting a portion of the cached chunk data as the read data from the cache memory when the read data is included in the cached chunk data.

Abstract: Provided are a steel cord and a single steel wire having excellent straightness quality for reinforcing tire and a method of manufacturing the steel cord and single steel wire. The steel cord and the single steel wire include a wire undergoing through a drawing process, a heating process performed in a state in which tension is applied to the wire, and a cooling process; and a winding portion on which the wire is wound, the winding portion having a diameter greater than a diameter of the wire, wherein, when an end of the wire that has been wound on the winding portion for six months to one year is fixed on a point and the wire is pulled down vertically to 400 mm, a distance between a first axis that is perpendicular to the point and an opposite end of the wire is 30 mm or less. The method of manufacturing the steel cord and single steel wire having excellent straightness quality for reinforcing tire includes: a wire preparing process, a heating process, a cooling process, and a winding process.

Abstract: A data storage device includes a storage, a buffer memory, and a controller. The controller is configured to control at least one of an input of data to and an output of data from the storage in response to a request transmitted from a host device. The controller is also configured to receive write data transmitted from the host device and cached in the buffer memory, encrypt the write data, and store the encrypted write data in the storage. The controller is further configured to receive read data read from the storage and cached in the buffer memory, decrypt the read data, and provide the decrypted read data to the host device.

Abstract: Disclosed are light emitting modules and automobile illumination devices including the same. The light emitting module comprises a module substrate, a light emitting device on the module substrate, and a light guide structure apart from the module substrate and in plan view surrounding the light emitting device. The light emitting device comprises a first pixel and a second pixel each including a light emitting diode (LED) chip that emits light whose wavelength falls within a range of blue color or ultraviolet ray, and a wavelength conversion material on a top surface of at least one of the first and second pixels.