Patents by Inventor Donald F. Canaperi
Donald F. Canaperi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11804378Abstract: A method for fabricating a planarized planarization layer for an integrated circuit device is described. A barrier layer is deposited over a planarization layer. Next, a liner layer is deposited on the barrier layer. An overburden layer is deposited on the liner layer. A first chemical mechanical polishing (CMP) process is performed on the overburden layer. A surface conversion process is performed on uncovered portions of a top surface of the planarization layer which are not protected by the polished overburden layer. A first wet etch is performed of the planarization layer. In embodiments, the first wet etch is selective to metal overburden layer as compared to the planarization layer. A second wet etch is performed removing the liner layer, the diffusion barrier layer and the metal overburden layer. In embodiments, the second wet etch is selective to the planarization layer as compared to the overburden layer.Type: GrantFiled: December 31, 2021Date of Patent: October 31, 2023Assignee: International Business Machines CorporationInventors: Raghuveer R Patlolla, Donald F Canaperi, Cornelius Brown Peethala, Chih-Chao Yang, Mary Breton
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Patent number: 11756786Abstract: A method of fabricating a dielectric film includes depositing a first precursor on a substrate. The first precursor includes a cyclic carbosiloxane group comprising a six-membered ring. The method also includes depositing a second precursor on the substrate. The first precursor and the second precursor form a preliminary film on the substrate, and the second precursor includes silicon, carbon, and hydrogen. The method further includes exposing the preliminary film to energy from an energy source to form a porous dielectric film.Type: GrantFiled: January 18, 2019Date of Patent: September 12, 2023Assignee: International Business Machines CorporationInventors: Benjamin D. Briggs, Donald F. Canaperi, Huy Cao, Thomas J. Haigh, Jr., Son Nguyen, Hosadurga Shobha, Devika Sil, Han You
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Publication number: 20230215734Abstract: A method for fabricating a planarized planarization layer for an integrated circuit device is described. A barrier layer is deposited over a planarization layer. Next, a liner layer is deposited on the barrier layer. An overburden layer is deposited on the liner layer. A first chemical mechanical polishing (CMP) process is performed on the overburden layer. A surface conversion process is performed on uncovered portions of a top surface of the planarization layer which are not protected by the polished overburden layer. A first wet etch is performed of the planarization layer. In embodiments, the first wet etch is selective to metal overburden layer as compared to the planarization layer. A second wet etch is performed removing the liner layer, the diffusion barrier layer and the metal overburden layer. In embodiments, the second wet etch is selective to the planarization layer as compared to the overburden layer.Type: ApplicationFiled: December 31, 2021Publication date: July 6, 2023Inventors: Raghuveer R. Patlolla, Donald F. Canaperi, Cornelius Brown Peethala, Chih-Chao Yang, Mary Breton
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Patent number: 11056418Abstract: A stacked semiconductor microcooler includes a first and second semiconductor microcooler. Each microcooler includes silicon fins extending from a silicon substrate. A metal layer may be formed upon the fins. The microcoolers may be positioned such that the fins of each microcooler are aligned. One or more microcoolers may be thermally connected to a surface of a coolant conduit that is thermally connected to an electronic device heat generating device, such as an integrated circuit (IC) chip, or the like. Heat from the electronic device heat generating device may transfer to the one or more microcoolers. A flow of cooled liquid may be introduced through the conduit and heat from the one or more microcoolers may transfer to the liquid coolant.Type: GrantFiled: December 13, 2019Date of Patent: July 6, 2021Assignee: International Business Machines CorporationInventors: Donald F. Canaperi, Daniel A. Corliss, Dario Goldfarb, Dinesh Gupta, Fee Li Lie, Kamal K. Sikka
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Patent number: 11049789Abstract: A stacked semiconductor microcooler includes a first microcooler and a second microcooler. The microcoolers may be positioned such that the fins of each microcooler are vertically aligned. The microcoolers may include an inlet passage to accept coolant and an outlet passage to expel the coolant. One or more microcoolers may be thermally connected to an electronic device heat generating device, such as an integrated circuit (IC) chip, or the like. Heat from the electronic device heat generating device may transfer to the one or more microcoolers. A flow of cooled liquid may be introduced through the passages and heat from the one or more microcoolers may transfer to the liquid coolant.Type: GrantFiled: December 13, 2019Date of Patent: June 29, 2021Assignee: International Business Machines CorporationInventors: Donald F. Canaperi, Daniel A. Corliss, Dario Goldfarb, Dinesh Gupta, Fee Li Lie, Kamal K. Sikka
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Patent number: 11031250Abstract: A semiconductor device and method of formation thereof. The semiconductor device includes a portion of a first material that abuts a portion of a second material and surrounds at least a portion of a semiconductor component. The first material has a first composition and a first index of refraction and is of a same type of material as the second material. The second material has a second composition and a second index of refraction. An opening in the first material exposes a portion of the semiconductor component.Type: GrantFiled: November 29, 2018Date of Patent: June 8, 2021Assignee: International Business Machines CorporationInventors: Mona A. Ebrish, Michael Rizzolo, Son Nguyen, Raghuveer R. Patlolla, Donald F. Canaperi
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Patent number: 10971675Abstract: Magnetic tunnel junction pillars are encapsulated by an oxidized diffusion barrier layer. Oxygen within the encapsulating material is used to oxidize metallic residue outside the pillars, converting the residue to a non-conductive material such as a metal oxide or metal oxynitride. Selective deposition of manganese on the metal layers of the pillars can be followed by oxidation of the manganese to form a manganese oxide diffusion barrier. Alternatively, manganese deposition can be followed by deposition of silicon dioxide and subsequent annealing to form a manganese silicate diffusion barrier.Type: GrantFiled: September 27, 2019Date of Patent: April 6, 2021Assignee: International Business Machines CorporationInventors: Son V. Nguyen, Alexander Reznicek, Donald F. Canaperi
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Patent number: 10937789Abstract: A semiconductor structure is provided in which a nanosheet device is formed laterally adjacent, but in proximity to, an embedded dynamic random access memory (eDRAM) cell. The eDRAM cell and the nanosheet device are connected by a doped polycrystalline semiconductor material that is formed during the epitaxial growth of doped single crystalline semiconductor source/drain regions of the nanosheet device. An eDRAM cut mask is used to remove unwanted semiconductor material from regions not including the eDRAM cell and the nanosheet device.Type: GrantFiled: June 7, 2018Date of Patent: March 2, 2021Assignee: International Business Machines CorporationInventors: Alexander Reznicek, Muthumanickam Sankarapandian, Donald F. Canaperi, Keith E. Fogel
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Patent number: 10832917Abstract: A method is presented for post chemical mechanical polishing (PCMP) clean for cleaning a chemically-mechanically polished semiconductor wafer. The method includes planarizing the semiconductor wafer, subjecting the semiconductor wafer to a de-oxygenated mixture of DI water and PCMP solution, and applying a de-oxygenated environment during the cleaning. The solution can be de-oxygenated by nitrogen degas or by introducing a reducing agent. The environment can be de-oxygenated by purging with an inert gas, such as nitrogen.Type: GrantFiled: June 9, 2017Date of Patent: November 10, 2020Assignee: International Business Machines CorporationInventors: Donald F. Canaperi, Pavan S. Chinthamanipeta, Raghuveer R. Patlolla, Cornelius B. Peethala
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Publication number: 20200234949Abstract: A method of fabricating a dielectric film includes depositing a first precursor on a substrate. The first precursor includes a cyclic carbosiloxane group comprising a six-membered ring. The method also includes depositing a second precursor on the substrate. The first precursor and the second precursor form a preliminary film on the substrate, and the second precursor includes silicon, carbon, and hydrogen. The method further includes exposing the preliminary film to energy from an energy source to form a porous dielectric film.Type: ApplicationFiled: January 18, 2019Publication date: July 23, 2020Inventors: Benjamin D. Briggs, Donald F. Canaperi, Huy Cao, Thomas J. Haigh, JR., Son Nguyen, Hosadurga Shobha, Devika Sil, Han You
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Publication number: 20200176263Abstract: A semiconductor device and method of formation thereof. The semiconductor device includes a portion of a first material that abuts a portion of a second material and surrounds at least a portion of a semiconductor component. The first material has a first composition and a first index of refraction and is of a same type of material as the second material. The second material has a second composition and a second index of refraction. An opening in the first material exposes a portion of the semiconductor component.Type: ApplicationFiled: November 29, 2018Publication date: June 4, 2020Inventors: Mona A. Ebrish, Michael Rizzolo, Son Nguyen, Raghuveer R. Patlolla, Donald F. Canaperi
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Publication number: 20200161216Abstract: A stacked semiconductor microcooler includes a first and second semiconductor microcooler. Each mircocooler includes silicon fins extending from a silicon substrate. A metal layer may be formed upon the fins. The microcoolers may be positioned such that the fins of each microcooler are aligned. One or more microcoolers may be thermally connected to a surface of a coolant conduit that is thermally connected to an electronic device heat generating device, such as an integrated circuit (IC) chip, or the like. Heat from the electronic device heat generating device may transfer to the one or more microcoolers. A flow of cooled liquid may be introduced through the conduit and heat from the one or more microcoolers may transfer to the liquid coolant.Type: ApplicationFiled: December 13, 2019Publication date: May 21, 2020Inventors: Donald F. Canaperi, Daniel A. Corliss, Dario Goldfarb, Dinesh Gupta, Fee Li Lie, Kamal K. Sikka
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Publication number: 20200118904Abstract: A stacked semiconductor microcooler includes a first microcooler and a second microcooler. The microcoolers may be positioned such that the fins of each microcooler are vertically aligned. The microcoolers may include an inlet passage to accept coolant and an outlet passage to expel the coolant. One or more microcoolers may be thermally connected to an electronic device heat generating device, such as an integrated circuit (IC) chip, or the like. Heat from the electronic device heat generating device may transfer to the one or more microcoolers. A flow of cooled liquid may be introduced through the passages and heat from the one or more microcoolers may transfer to the liquid coolant.Type: ApplicationFiled: December 13, 2019Publication date: April 16, 2020Inventors: Donald F. Canaperi, Daniel A. Corliss, Dario Goldfarb, Dinesh Gupta, Fee Li Lie, Kamal K. Sikka
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Publication number: 20200051886Abstract: A semiconductor microcooler is fabricated by forming fins in a semiconductor substrate and forming a metal layer upon the fins. A stacked microcooler may be formed by stacking a plurality of semiconductor microcoolers. The microcoolers may be positioned such that the fins of each microcooler are vertically aligned. The microcoolers may include an inlet passage to accept coolant and an outlet passage to expel the coolant. One or more microcoolers may be thermally connected to an electronic device heat generating device, such as an integrated circuit (IC) chip, or the like. Heat from the electronic device heat generating device may transfer to the one or more microcoolers. A flow of cooled liquid may be introduced through the passages and heat from the one or more microcoolers may transfer to the liquid coolant.Type: ApplicationFiled: August 13, 2018Publication date: February 13, 2020Inventors: Donald F. Canaperi, Daniel A. Corliss, Dario Goldfarb, Dinesh Gupta, Fee Li Lie, Kamal K. Sikka
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Publication number: 20200051896Abstract: A semiconductor microcooler is fabricated by forming fins in a semiconductor substrate and forming a metal layer upon the fins. A stacked microcooler may be formed by stacking a plurality of semiconductor microcoolers. The microcoolers may be positioned such that the fins of each microcooler are aligned. One or more microcoolers may be thermally connected to a surface of a coolant conduit that is thermally connected to an electronic device heat generating device, such as an integrated circuit (IC) chip, or the like. Heat from the electronic device heat generating device may transfer to the one or more microcoolers. A flow of cooled liquid may be introduced through the conduit and heat from the one or more microcoolers may transfer to the liquid coolant.Type: ApplicationFiled: August 13, 2018Publication date: February 13, 2020Inventors: Donald F. Canaperi, Daniel A. Corliss, Dario Goldfarb, Dinesh Gupta, Fee Li Lie, Kamal K. Sikka
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Patent number: 10553516Abstract: A semiconductor microcooler is fabricated by forming fins in a semiconductor substrate and forming a metal layer upon the fins. A stacked microcooler may be formed by stacking a plurality of semiconductor microcoolers. The microcoolers may be positioned such that the fins of each microcooler are vertically aligned. The microcoolers may include an inlet passage to accept coolant and an outlet passage to expel the coolant. One or more microcoolers may be thermally connected to an electronic device heat generating device, such as an integrated circuit (IC) chip, or the like. Heat from the electronic device heat generating device may transfer to the one or more microcoolers. A flow of cooled liquid may be introduced through the passages and heat from the one or more microcoolers may transfer to the liquid coolant.Type: GrantFiled: August 13, 2018Date of Patent: February 4, 2020Assignee: International Business Machines CorporationInventors: Donald F. Canaperi, Daniel A. Corliss, Dario Goldfarb, Dinesh Gupta, Fee Li Lie, Kamal K. Sikka
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Patent number: 10553522Abstract: A semiconductor microcooler is fabricated by forming fins in a semiconductor substrate and forming a metal layer upon the fins. A stacked microcooler may be formed by stacking a plurality of semiconductor microcoolers. The microcoolers may be positioned such that the fins of each microcooler are aligned. One or more microcoolers may be thermally connected to a surface of a coolant conduit that is thermally connected to an electronic device heat generating device, such as an integrated circuit (IC) chip, or the like. Heat from the electronic device heat generating device may transfer to the one or more microcoolers. A flow of cooled liquid may be introduced through the conduit and heat from the one or more microcoolers may transfer to the liquid coolant.Type: GrantFiled: August 13, 2018Date of Patent: February 4, 2020Assignee: International Business Machines CorporationInventors: Donald F. Canaperi, Daniel A. Corliss, Dario Goldfarb, Dinesh Gupta, Fee Li Lie, Kamal K. Sikka
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Publication number: 20200028069Abstract: Magnetic tunnel junction pillars are encapsulated by an oxidized diffusion barrier layer. Oxygen within the encapsulating material is used to oxidize metallic residue outside the pillars, converting the residue to a non-conductive material such as a metal oxide or metal oxynitride. Selective deposition of manganese on the metal layers of the pillars can be followed by oxidation of the manganese to form a manganese oxide diffusion barrier. Alternatively, manganese deposition can be followed by deposition of silicon dioxide and subsequent annealing to form a manganese silicate diffusion barrier.Type: ApplicationFiled: September 27, 2019Publication date: January 23, 2020Inventors: Son V. Nguyen, Alexander Reznicek, Donald F. Canaperi
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Publication number: 20190378842Abstract: A semiconductor structure is provided in which a nanosheet device is formed laterally adjacent, but in proximity to, an embedded dynamic random access memory (eDRAM) cell. The eDRAM cell and the nanosheet device are connected by a doped polycrystalline semiconductor material that is formed during the epitaxial growth of doped single crystalline semiconductor source/drain regions of the nanosheet device. An eDRAM cut mask is used to remove unwanted semiconductor material from regions not including the eDRAM cell and the nanosheet device.Type: ApplicationFiled: June 7, 2018Publication date: December 12, 2019Inventors: Alexander Reznicek, Muthumanickam Sankarapandian, Donald F. Canaperi, Keith E. Fogel
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Patent number: 10468585Abstract: Magnetic tunnel junction pillars are encapsulated by an oxidized diffusion barrier layer. Oxygen within the encapsulating material is used to oxidize metallic residue outside the pillars, converting the residue to a non-conductive material such as a metal oxide or metal oxynitride. Selective deposition of manganese on the metal layers of the pillars can be followed by oxidation of the manganese to form a manganese oxide diffusion barrier. Alternatively, manganese deposition can be followed by deposition of silicon dioxide and subsequent annealing to form a manganese silicate diffusion barrier.Type: GrantFiled: May 31, 2018Date of Patent: November 5, 2019Assignee: International Business Machines CorporationInventors: Son V. Nguyen, Alexander Reznicek, Donald F. Canaperi