Abstract: A device and a method for forming a device are disclosed. The device includes a substrate with a high voltage (HV) device region. The HV device region is defined with first and second device isolation regions and an internal dielectric region which are shallow trench isolation (STI) regions. A HV transistor is disposed in the HV device region. The HV transistor includes a gate dielectric layer on the substrate, a gate disposed on the gate dielectric layer, and a source region disposed in the substrate adjacent to the gate and first device isolation region while a drain region disposed in the substrate adjacent to the second device isolation region. A drift well and a body well are disposed in the substrate. At least one buried RESURF region is disposed under the internal dielectric region.

Abstract: Devices and methods of forming a device are disclosed. The method includes providing a wafer that includes a center insulator layer sandwiched by a top substrate and a bottom substrate. Both sides of the wafer are patterned and etched in sequence to form deep trenches in both substrates. A conductive seed layer is formed on both sides of the wafer in sequence to cover all exposed areas. Both sides of the wafer are electroplated simultaneously to fill both deep trenches with a conductive material. Both sides of the wafer are polished in sequence to form a coplanar surface. A protective layer is deposited on both sides of the wafer in sequence. Selective portions of the protective layer on both sides are patterned and etched in sequence to expose micro bump bonding areas. Micro bumps are formed on both sides of the wafer in sequence to facilitate electrical connection.

Abstract: Isolation structures for isolating semiconductor devices from a substrate include floor isolation regions buried within the substrate and one or more trenches extending from a surface of the substrate to the buried floor isolation region.

Abstract: An isolation structure formed in a semiconductor substrate of a first conductivity type includes a region of a second conductivity type opposite to the first conductivity type. The region of the second conductivity type is saucer-shaped and has a floor portion substantially parallel to the top surface of the substrate and a sloped sidewall portion. The sloped sidewall portion extends downward from the top surface of the substrate at an oblique angle and merges with the floor portion. The floor portion and the sloped sidewall portion together form an isolated pocket of the substrate.

Abstract: An isolation structure formed in a semiconductor substrate of a first conductivity type includes a floor isolation region of a second conductivity type opposite to the first conductivity type submerged in the substrate. A first trench extends downward from a surface of the substrate and overlaps onto the floor isolation region. The first trench includes walls lined with a dielectric material and contains a conductive material. The first trench and the floor isolation region electrically isolate a pocket of the first conductivity type from the substrate.

Abstract: A method for fabricating a high-voltage transistor with an extended drain region includes forming in a semiconductor substrate of a first conductivity type, first and second trenches that define a mesa having respective first and second sidewalls; then partially filling each of the trenches with a dielectric material that covers the first and second sidewalls. The remaining portions of the trenches are then filled with a conductive material to form first and second field plates. Source and body regions are formed in an upper portion of the mesa, with the body region separating the source from a lower portion of the mesa. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: Isolation structures for isolating semiconductor devices from a substrate include floor isolation regions buried within the substrate and one or more trenches extending from a surface of the substrate to the buried floor isolation region.

Abstract: The embodiments of the present disclosure disclose a trench-gate MOSFET device and the method for making the trench-gate MOSFET device. The trench-gate MOSFET device comprises a curving dopant profile formed between the body region and the epitaxial layer so that the portion of the body region under the source metal contact has a smaller vertical thickness than the other portion of the body region. The trench-gate MOSFET device in accordance with the embodiments of the present disclosure has improved UIS capability compared with the traditional trench-gate MOSFET device.

Abstract: A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall isolation regions. Both the trench and the sidewall isolation regions may be annular and enclose an isolated pocket of the substrate. The isolation structures are formed by modular implant and etch processes that do not include significant thermal processing or diffusion of dopants so that the resulting structures are compact and may be tightly packed in the surface of the substrate.

Abstract: An Electro-Static Discharge (ESD) protection device is formed in an isolated region of a semiconductor substrate. The ESD protection device may be in the form of a MOS or bipolar transistor or a diode. The isolation structure may include a deep implanted floor layer and one or more implanted wells that laterally surround the isolated region. The isolation structure and ESD protection devices are fabricated using a modular process that includes virtually no thermal processing. Since the ESD device is isolated, two or more ESD devices may be electrically “stacked” on one another such that the trigger voltages of the devices are added together to achieve a higher effective trigger voltage.

Abstract: A high-voltage transistor includes a drain, a source, and one or more drift regions extending from the drain toward the source. A field plate member laterally surrounds the drift regions and is insulated from the drift regions by a dielectric layer. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: A lateral MOSFET formed in a substrate of a first conductivity type includes a gate formed atop a gate dielectric layer over a surface of the substrate, a drain region of a second conductivity type, a source region of a second conductivity type, and a body region of the first conductivity type which extends under the gate. The body region may have a non-monotonic vertical doping profile with a portion located deeper in the substrate having a higher doping concentration than a portion located shallower in the substrate. The lateral MOSFET is drain-centric, with the source region and a dielectric-filled trench surrounding the drain region.

Abstract: An isolation structure for a semiconductor device comprises a floor isolation region, a dielectric filled trench above the floor isolation region and a sidewall isolation region extending downward from the bottom of the trench to the floor isolation region. This structure provides a relatively deep isolated pocket in a semiconductor substrate while limiting the depth of the trench that must be etched in the substrate. An isolated junction field-effect transistor is formed in the isolated pocket.

Abstract: A method for fabricating a high-voltage transistor with an extended drain region includes forming in a semiconductor substrate of a first conductivity type, first and second trenches that define a mesa having respective first and second sidewalls; then partially filling each of the trenches with a dielectric material that covers the first and second sidewalls. The remaining portions of the trenches are then filled with a conductive material to form first and second field plates. Source and body regions are formed in an upper portion of the mesa, with the body region separating the source from a lower portion of the mesa. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).

Abstract: A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall isolation regions. Both the trench and the sidewall isolation regions may be annular and enclose an isolated pocket of the substrate. The isolation structures are formed by modular implant and etch processes that do not include significant thermal processing or diffusion of dopants so that the resulting structures are compact and may be tightly packed in the surface of the substrate.

Abstract: A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall isolation regions. Both the trench and the sidewall isolation regions may be annular and enclose an isolated pocket of the substrate. The isolation structures are formed by modular implant and etch processes that do not include significant thermal processing or diffusion of dopants so that the resulting structures are compact and may be tightly packed in the surface of the substrate.

Abstract: An isolated diode comprises a floor isolation region, a dielectric-filled trench and a sidewall region extending from a bottom of the trench at least to the floor isolation region. The floor isolation region, dielectric-filled trench and a sidewall region are comprised in one terminal (anode or cathode) of the diode and together form an isolated pocket in which the other terminal of the diode is formed. In one embodiment the terminals of the diode are separated by a second dielectric-filled trench and sidewall region.

Abstract: A method for fabricating a high-voltage transistor with an extended drain region includes forming in a semiconductor substrate of a first conductivity type, first and second trenches that define a mesa having respective first and second sidewalls; then partially filling each of the trenches with a dielectric material that covers the first and second sidewalls. The remaining portions of the trenches are then filled with a conductive material to form first and second field plates. Source and body regions are formed in an upper portion of the mesa, with the body region separating the source from a lower portion of the mesa. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).

Abstract: An Electro-Static Discharge (ESD) protection device is formed in an isolated region of a semiconductor substrate. The ESD protection device may be in the form of a MOS or bipolar transistor or a diode. The isolation structure may include a deep implanted floor layer and one or more implanted wells that laterally surround the isolated region. The isolation structure and ESD protection devices are fabricated using a modular process that includes virtually no thermal processing. Since the ESD device is isolated, two or more ESD devices may be electrically “stacked” on one another such that the trigger voltages of the devices are added together to achieve a higher effective trigger voltage.

Abstract: A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall isolation regions. Both the trench and the sidewall isolation regions may be annular and enclose an isolated pocket of the substrate. The isolation structures are formed by modular implant and etch processes that do not include significant thermal processing or diffusion of dopants so that the resulting structures are compact and may be tightly packed in the surface of the substrate.