Patents by Inventor Donald S. Gardner

Donald S. Gardner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Forming electroplated inductor structures for integrated circuits
    Patent number: 8029922
    Abstract: Methods and associated structures of forming microelectronic devices are described. Those methods may include forming a magnetic material on a substrate, wherein the magnetic material comprises rhenium, cobalt, iron and phosphorus, and annealing the magnetic material at a temperature below about 330 degrees Celsius, wherein the coercivity of the annealed magnetic material is below about 1 Oersted.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: October 4, 2011
    Assignee: Intel Corporation
    Inventors: Paul McCloskey, Donald S. Gardner, Brice Jamieson, Saibal Roy, Terence O'Donnell
  • Method and apparatus for optical signaling
    Patent number: 7991302
    Abstract: A method and apparatus for optical signaling. In one embodiment, a laser driver converts a digital voltage sequence to a current signal having a bias mode adjustable by a bias control and a modulation mode adjustable by a modulation control. A laser generates an optical signal responsive to the current signal of the laser driver. In one embodiment, a photo-detector receives an optical signal and generates a single ended current signal. A transimpedance amplifier circuit converts the single ended current signal to a differential voltage signal. A clock recovery circuit generates an aligned clock signal and a sampler circuit uses the aligned clock signal to retrieve a digital voltage sequence.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: August 2, 2011
    Assignee: Intel Corporation
    Inventors: Jianping Xu, Fabrice Paillet, Tanay Karnik, Donald S. Gardner
  • Integrated transformer
    Patent number: 7982574
    Abstract: A transformer comprises a substrate comprising a semiconductor material, a first conductor over the substrate, a second conductor over the substrate, and a magnetic layer over the substrate. The first conductor defines a generally spiral-shaped signal path having at least one turn. The second conductor defines a generally spiral-shaped signal path having at least one turn.
    Type: Grant
    Filed: August 2, 2010
    Date of Patent: July 19, 2011
    Assignee: Intel Corporation
    Inventor: Donald S. Gardner
  • ON-DIE MICRO-TRANSFORMER STRUCTURES WITH MAGNETIC MATERIALS
    Publication number: 20110068887
    Abstract: Some embodiments include a die having a transformer. The transformer includes windings formed from a set of lines, such that no two lines belonging to any one winding are nearest neighbors. The lines are formed within one layer on the die. Other embodiments are described.
    Type: Application
    Filed: November 29, 2010
    Publication date: March 24, 2011
    Inventors: Donald S. Gardner, Peter Hazucha, Gerhard Schrom
  • Forming inductor and transformer structures with magnetic materials using damascene processing for integrated circuits
    Patent number: 7867787
    Abstract: Methods and associated structures of forming microelectronic devices are described. Those methods may include forming a first layer of magnetic material and at least one via structure disposed in a first dielectric layer, forming a second dielectric layer disposed on the first magnetic layer, forming at least one conductive structure disposed in the second dielectric layer, forming a third layer of dielectric material disposed on the conductive structure, forming a second layer of magnetic material disposed in the third layer of dielectric material and in the second layer of dielectric material, wherein the first and second layers of the magnetic material are coupled to one another.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: January 11, 2011
    Assignee: Intel Corporation
    Inventors: Donald S. Gardner, Gerhard Schrom, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • FORMING INDUCTOR AND TRANSFORMER STRUCTURES WITH MAGNETIC MATERIALS USING DAMASCENE PROCESSING FOR INTEGRATED CIRCUITS
    Publication number: 20110001202
    Abstract: Methods and associated structures of forming microelectronic devices are described. Those methods may include forming a first layer of magnetic material and at least one via structure disposed in a first dielectric layer, forming a second dielectric layer disposed on the first magnetic layer, forming at least one conductive structure disposed in the second dielectric layer, forming a third layer of dielectric material disposed on the conductive structure, forming a second layer of magnetic material disposed in the third layer of dielectric material and in the second layer of dielectric material, wherein the first and second layers of the magnetic material are coupled to one another.
    Type: Application
    Filed: September 15, 2010
    Publication date: January 6, 2011
    Inventors: Donald S. Gardner, Gerhard Schrom, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • On-die micro-transformer structures with magnetic materials
    Patent number: 7852185
    Abstract: A transformer integrated on a die, the transformer comprising a set of conductive lines formed on the die within one layer and interconnected among each other so that no two lines belonging to any one winding are nearest neighbors. The set of conductive lines is surrounded by a magnetic material, which may be amorphous CoZrTa, CoFeHfO, CoAlO, FeSiO, CoFeAlO, CoNbTa, CoZr, and other amorphous cobalt alloys. The transformer may be operated at frequencies higher than 10 MHz and as high as 1 GHz, with relatively low resistance and relatively high magnetic coupling between the windings.
    Type: Grant
    Filed: May 5, 2003
    Date of Patent: December 14, 2010
    Assignee: Intel Corporation
    Inventors: Donald S. Gardner, Peter Hazucha, Gerhard Schrom
  • INTEGRATED TRANSFORMER
    Publication number: 20100295649
    Abstract: A transformer comprises a substrate comprising a semiconductor material, a first conductor over the substrate, a second conductor over the substrate, and a magnetic layer over the substrate. The first conductor defines a generally spiral-shaped signal path having at least one turn. The second conductor defines a generally spiral-shaped signal path having at least one turn.
    Type: Application
    Filed: August 2, 2010
    Publication date: November 25, 2010
    Inventor: Donald S. Gardner
  • MAGNETIC MICROINDUCTORS FOR INTEGRATED CIRCUIT PACKAGING
    Publication number: 20100259911
    Abstract: Magnetic microinductors formed on semiconductor packages are provided. The magnetic microinductors are formed as one or more layers of coplanar magnetic material on a package substrate. Conducting vias extend perpendicularly through the plane of the magnetic film. The magnetic film is a layer of isotropic magnetic material or a plurality of layers of anisotropic magnetic material having differing hard axes of magnetization.
    Type: Application
    Filed: June 25, 2010
    Publication date: October 14, 2010
    Inventors: Donald S. Gardner, Larry E. Mosley
  • Integrated transformer
    Patent number: 7791447
    Abstract: A transformer comprises a substrate comprising a semiconductor material, a first conductor over the substrate, a second conductor over the substrate, and a magnetic layer over the substrate. The first conductor defines a generally spiral-shaped signal path having at least one turn. The second conductor defines a generally spiral-shaped signal path having at least one turn.
    Type: Grant
    Filed: September 25, 2008
    Date of Patent: September 7, 2010
    Assignee: Intel Corporation
    Inventor: Donald S. Gardner
  • Power management integrated circuit
    Publication number: 20100219516
    Abstract: An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.
    Type: Application
    Filed: February 24, 2010
    Publication date: September 2, 2010
    Inventors: Siva G. Narendra, James W. Tschanz, Howard A. Wilson, Donald S. Gardner, Peter Hazucha, Gerhard Schrom, Tanay Karnik, Nitin Borkar, Vivek K. De, Shekhar Y. Borkar
  • ANTENNA STRUCTURE
    Publication number: 20100141533
    Abstract: An antenna structure that includes a magnetic film coated on a textured backside of an antenna substrate to reduce the size of antenna from an average size of the antenna for a predetermined frequency band.
    Type: Application
    Filed: December 4, 2008
    Publication date: June 10, 2010
    Inventors: DONALD S. GARDNER, Seong-Youp Suh
  • Laminated magnetic material for inductors in integrated circuits
    Patent number: 7719084
    Abstract: An embodiment is an inductor that may include a laminated material structure to decrease eddy currents therein that may limit the operation of the inductor at high frequency. An embodiment may employ electroless plating techniques to form a layer or layers of magnetic material within the laminated material structure, and in particular those magnetic layers adjacent to insulator layers.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventors: Donald S. Gardner, Gerhard Schrom, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • Integrated inductor
    Publication number: 20100118501
    Abstract: An inductor and multiple inductors embedded in a substrate (e.g., IC package substrate, board substrate, and/or other substrate) is provided herein.
    Type: Application
    Filed: November 3, 2009
    Publication date: May 13, 2010
    Inventors: Peter Hazucha, Edward Burton, Trang T. Nguyen, Gerhard Schrom, Fabrice Paillet, Kaladhar Radhakrishnan, Donald S. Gardner, Sung T. Moon, Tanay Karnik
  • CPU POWER DELIVERY SYSTEM
    Publication number: 20100115301
    Abstract: A central processing unit (CPU) is disclosed. The CPU includes a CPU die; and a voltage regulator die bonded to the CPU die in a three dimensional packaging layout.
    Type: Application
    Filed: January 8, 2010
    Publication date: May 6, 2010
    Inventors: Siva G. Narendra, Howard A. Wilson, Donald S. Gardner, Peter Hazucha, Gerhard Schrom, Tanay Karnik, Nitin Borkar, Vivek K. De, Shekhar Y. Borkar
  • Control of eddy currents in magnetic vias for inductors and transformers in integrated circuits
    Patent number: 7710234
    Abstract: An embodiment is a magnetic via. More specifically, an embodiment is a magnetic via that increases the inductance of, for example, an integrated inductor or transformer while mitigating eddy currents therein that may limit the operation of the inductor or transformer at high frequency.
    Type: Grant
    Filed: August 6, 2008
    Date of Patent: May 4, 2010
    Assignee: Intel Corporation
    Inventors: Donald S. Gardner, Gerhard Schrom, Peter Hazucha, Fabrice Paillet, Tanay Kamik
  • CPU power delivery system
    Patent number: 7698576
    Abstract: A central processing unit (CPU) is disclosed. The CPU includes a CPU die; and a voltage regulator die bonded to the CPU die in a three dimensional packaging layout.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: April 13, 2010
    Assignee: Intel Corporation
    Inventors: Siva G. Narendra, Howard A. Wilson, Donald S. Gardner, Peter Hazucha, Gerhard Schrom, Tanay Karnik, Nitin Borkar, Vivek K. De, Shekhar Y. Borkar
  • Power management integrated circuit
    Patent number: 7671456
    Abstract: An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.
    Type: Grant
    Filed: July 3, 2007
    Date of Patent: March 2, 2010
    Assignee: Intel Corporation
    Inventors: Siva G. Narendra, James W. Tschantz, Howard A. Wilson, Donald S. Gardner, Peter Hazucha, Gerhard Schrom, Tanay Karnik, Nitin Borkar, Vivek K. De, Shekhar Y. Borkar
  • Integrated inductor
    Patent number: 7636242
    Abstract: An inductor and multiple inductors embedded in a substrate (e.g., IC package substrate, board substrate, and/or other substrate) is provided herein.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: December 22, 2009
    Assignee: Intel Corporation
    Inventors: Peter Hazucha, Edward Burton, Trang T. Nguyen, Gerhard Schrom, Fabrice Paillet, Kaladhar Radhakrishnan, Donald S. Gardner, Sung T. Moon, Tanay Karnik
  • SLOTTED MAGNETIC MATERIAL FOR INTEGRATED CIRCUIT INDUCTORS
    Publication number: 20090207576
    Abstract: An embodiment is an inductor that may include a slotted magnetic material to decrease eddy currents therein that may limit the operation of the inductor at high frequency. An embodiment may employ electro- or electroless plating techniques to form a layer or layers of magnetic material within the slotted magnetic material structure, and in particular those magnetic material layers adjacent to insulator layers.
    Type: Application
    Filed: March 18, 2009
    Publication date: August 20, 2009
    Applicant: INTEL CORPORATION
    Inventors: Donald S. Gardner, Gerhard Schrom, Peter Hazucha, Fabrice Paillet, Tanay Karnik