Abstract: An electronic device includes a memory controller; a first memory device coupled to the memory controller; a second memory device coupled to the memory controller, the second memory device being a different type of memory from the first memory device; and a conversion circuit between the memory controller and the second memory device. The memory controller is configured to send a first command and first data to the first memory device according to a first timing scheme to access the first memory device, and send a second command and a packet to the conversion circuit according to the first timing scheme to access the second memory device. The conversion circuit is configured to receive the second command and the packet, and access the second memory device based on the second command and the packet.

Abstract: In a method of operating a memory system including a memory device, a memory controller and a host according to example embodiments, a hardware is initialized based on a fail information and a boot code stored in a nonvolatile memory of a volatile memory and the nonvolatile memory included in the memory device. A host processes data in an internal memory included in the memory controller and a safe region included in the memory device based on the fail information. Using the fail information, the method of operating the memory system according to example embodiments increases the performance of the whole system including the memory system.

Abstract: A memory system includes a memory controller, a memory cell array, a location information storage unit, an address mapping table, an address conversion unit, and a mapping information calculation unit. The memory controller generates a logical address signal and an address re-mapping command. The memory cell array includes a plurality of logic blocks. The location information storage unit stores location information corresponding to faulty memory cells included in the memory cell array. The address mapping table stores address mapping information. The address conversion unit converts the logical address signal to a physical address signal corresponding to the memory cell array based on the address mapping information. The mapping information calculation unit generates the address mapping information to reduce the number of logic blocks including the faulty memory cells based on the location information upon the mapping information calculation unit receiving the address re-mapping command.

Abstract: A memory system includes a read-only memory (ROM), a main memory and a processor. The ROM stores a basic input/output system (BIOS). The main memory includes a fail address table which stores at least one fail address designating a memory cell row having at least one defective cell. The processor receives fail information of the at least one fail address from the main memory and loads data associated with a booting operation of the memory system in a safe area of the main memory by avoiding a fail area corresponding to the at least one fail address during power-on operation while a power is applied to the memory system. The data associated with the booting operation is stored in a storage device.

Abstract: A method of repairing a memory device including a boot memory region, a normal memory region, and a redundant memory region, the redundant memory region including a plurality of repair memory units, includes repairing the boot memory region by performing at least one of excluding first fault memory units of the boot memory region from use as storage and replacing the first fault memory units with boot repair memory units of the repair memory units, each of the first fault memory units having at least one fault memory cell; and after the repairing the boot memory region, repairing the normal memory region by performing at least one of excluding second fault memory units from use as storage and replacing the second fault memory units with normal repair memory units of the repair memory units.

Abstract: In a method of operating a memory system including a memory device and a memory controller, the memory controller reads fail information from a fail info region included in the memory device. The memory controller maps a logical address related to a program to a physical address of a safe region based on the fail information to store the program in the safe region except the fail info region and a fail region included in the memory device. The memory controller loads the program into the safe region of the memory device according to the address mapping. The method of operating the memory system according to example embodiments increases the performance of the memory system.

Abstract: A hybrid memory system includes a central processing unit, a storage device configured to store user data and code data, and a main memory including a volatile memory and a nonvolatile memory, the main memory being configured to receive data necessary to perform an operation of the central processing unit from the storage device and to store the data, a part of the volatile memory being allocated for a cache for data stored in the nonvolatile memory.

Abstract: A memory apparatus includes a local bus, a plurality of non-volatile memories, a first buffer, and a main controller. The non-volatile memories share the local bus. The first buffer is connected to the plurality of non-volatile memories via the local bus. The first buffer buffers data stored in the plurality of non-volatile memories. The main controller is configured to generate a control signal for controlling the first buffer to buffer data stored in a source memory of the plurality of non-volatile memories and transmit the data to a target memory.

Abstract: A multi-chip memory system comprises source and target memory devices, a memory controller configured to control operations of the source and target memory devices, and a data bus configured for data transfer of the memory controller and the source and target memory devices. The memory controller controls the source memory device to perform a read operation to output data to the data bus. Concurrently, the memory controller controls the target memory device to store the data from the data bus.

Abstract: A semiconductor memory device having a multi-chip package structure providing active termination control. The semiconductor memory device includes first and second memory chips sharing a data I/O bus. The first memory chip includes a first chip enable (CE) port determining whether the first memory chip is activated, and a second CE port monitoring whether the second memory chip is activated. An active termination unit is turned ON only when the first and second chips are deactivated.

Abstract: A multi-level cell (MLC) phase-change memory device divides data into data groups each comprising multiple bits of data, and stores each of the data groups in a selected phase-change memory cell. A data group is stored in a selected phase-change memory cell by applying a pulse current to the selected phase-change memory cell with a pulse current characteristic corresponding to a data value of the data group. The pulse current characteristic can comprise, for instance, a magnitude, downward slope, or duration of the pulse current. Data is read from a selected phase-change memory cell by sensing a voltage of a bitline connected to the selected phase-change memory cell and comparing the sensed voltage simultaneously with a plurality of reference voltages.

Abstract: A hybrid memory system includes a central processing unit, a storage device configured to store user data and code data, and a main memory including a volatile memory and a nonvolatile memory, the main memory being configured to receive data necessary to perform an operation of the central processing unit from the storage device and to store the data, a part of the volatile memory being allocated for a cache for data stored in the nonvolatile memory.

Abstract: A system includes a memory controller adapted to output address signals, command signals and select signals; a plurality of memory modules; and a plurality of buses each corresponding to one of the memory modules. Each bus is adapted to transmit corresponding ones of the address signals, the command signals, and the select signals to the corresponding memory module. Each of the memory modules includes: a plurality of memory devices; and a register adapted to receive and buffer the corresponding command and address signals transmitted to the memory module, and adapted to transmit the buffered command signal to the memory devices which are to be accessed, in response to the corresponding select signal for accessing the memory devices.

Abstract: A memory apparatus includes a local bus, a plurality of non-volatile memories, a first buffer, and a main controller. The non-volatile memories share the local bus. The first buffer is connected to the plurality of non-volatile memories via the local bus. The first buffer buffers data stored in the plurality of non-volatile memories. The main controller is configured to generate a control signal for controlling the first buffer to buffer data stored in a source memory of the plurality of non-volatile memories and transmit the data to a target memory.

Abstract: The memory system, memory device, memory controller and method may have a reduced power consumption. The memory system, memory device, memory controller and method may transition a data strobe signal to a valid logic level during a standby state. The valid logic level may be less than a logic level associated with a higher impedance level, such as when a bus may be turned off or connected to a ground voltage. A delay locked circuit need not be used in the memory device.

Abstract: A semiconductor device includes a plurality of non-volatile memory cells connected between a plurality of word lines and a plurality of bit lines, respectively, and a sense amplifier block for sensing and amplifying a signal of a word line among the plurality of word lines.

Abstract: A multi-chip memory system comprises source and target memory devices, a memory controller configured to control operations of the source and target memory devices, and a data bus configured for data transfer of the memory controller and the source and target memory devices. The memory controller controls the source memory device to perform a read operation to output data to the data bus. Concurrently, the memory controller controls the target memory device to store the data from the data bus.

Abstract: A memory controller includes a memory capacity setting circuit and an address selecting circuit. The memory capacity setting circuit is configured to set a valid memory capacity of a memory device based on a defective cell information signal, and generate a valid memory capacity signal based on the valid memory capacity. The address selecting circuit is configured to disable an address signal corresponding to a memory block having a defective cell, and generate a selection address signal based on the valid memory capacity signal and the disabled address signal. A non-defective cell in a memory cell array is activated based on the selection address signal and a command signal.

Abstract: A multi-level cell (MLC) phase-change memory device divides data into data groups each comprising multiple bits of data, and stores each of the data groups in a selected phase-change memory cell. A data group is stored in a selected phase-change memory cell by applying a pulse current to the selected phase-change memory cell with a pulse current characteristic corresponding to a data value of the data group. The pulse current characteristic can comprise, for instance, a magnitude, downward slope, or duration of the pulse current. Data is read from a selected phase-change memory cell by sensing a voltage of a bitline connected to the selected phase-change memory cell and comparing the sensed voltage simultaneously with a plurality of reference voltages.

Abstract: A semiconductor memory device having a multi-chip package structure providing active termination control. The semiconductor memory device includes first and second memory chips sharing a data I/O bus. The first memory chip includes a first chip enable (CE) port determining whether the first memory chip is activated, and a second CE port monitoring whether the second memory chip is activated. An active termination unit is turned ON only when the first and second chips are deactivated.