Abstract: Integrated circuit memory devices include a data latch circuit having a data input, a control input and a clock input, and a strobe signal input buffer. The strobe signal input buffer is preferably responsive to a data strobe signal and an indication signal. The strobe signal input buffer operates as a filter by selectively passing an inactive-to-active transition of the data strobe signal to the control input of the data latch when the indication signal is active, while blocking passage of the inactive-to-active transition of the data strobe signal to the control input when the indication signal is inactive. These filtering operations are preferably performed to inhibit the occurrence of data errors when excessive timing skew is present between a system clock and a data strobe signal at a given rate of speed. Accordingly, the operating speeds of memory devices according to embodiments of the present invention may be reliably increased.

Abstract: A synchronous DRAM (SDRAM) having a posted column access strobe (CAS) latency and a method of controlling CAS latency are provided. In order to control a delay time from the application of a CAS command and a column address to the beginning of memory, reading or writing operations in units of clock cycles, a first method of programing the delay time as a mode register set (MRS) and a second method of detecting the delay time using an internal signal and an external signal, are provided. In the second method, the SDRAM can include a counter for controlling the CAS latency. This counter controls the CAS latency of the SDRAM by generating a signal for controlling the CAS latency according to the number of clock cycles of a clock signal from the generation of a row access command to a column access command in the same memory bank and reading the signal.