Abstract: A memory device includes a first metal layer and a first metal oxide layer coupled to the first metal layer. The memory device includes a second metal oxide layer coupled to the first metal oxide layer and a second metal layer coupled to the second metal oxide layer. The formation of the first metal oxide layer has a Gibbs free energy that is lower than the Gibbs free energy for the formation of the second metal oxide layer.

Abstract: A memory device includes a first metal layer and a first metal oxide layer coupled to the first metal layer. The memory device includes a second metal oxide layer coupled to the first metal oxide layer and a second metal layer coupled to the second metal oxide layer.

Abstract: A resistive memory device is disclosed. The memory device comprises one or more metal oxide layers. An oxygen vacancy or ion concentrations of the one or more metal oxide layer is controlled in the formation and the operation of the memory device to provide robust memory operation.

Abstract: A memory device includes a first metal layer and a first metal oxide layer coupled to the first metal layer. The memory device includes a second metal oxide layer coupled to the first metal oxide layer and a second metal layer coupled to the second metal oxide layer. The formation of the first metal oxide layer has a Gibbs free energy that is lower than the Gibbs free energy for the formation of the second metal oxide layer.

Abstract: A memory device includes a first metal layer and a first metal oxide layer coupled to the first metal layer. The memory device includes a second metal oxide layer coupled to the first metal oxide layer and a second metal layer coupled to the second metal oxide layer.

Abstract: A memory device includes a first metal layer and a first metal oxide layer coupled to the first metal layer. The memory device includes a second metal oxide layer coupled to the first metal oxide layer and a second metal layer coupled to the second metal oxide layer. The formation of the first metal oxide layer has a Gibbs free energy that is lower than the Gibbs free energy for the formation of the second metal oxide layer.

Abstract: A multilayered integrated optical and circuit device. The device has a first substrate comprising at least one integrated circuit chip thereon, which has a cell region and a peripheral region. Preferably, the peripheral region has a bonding pad region, which has one or more bonding pads and an antistiction region surrounding each of the one or more bonding pads. The device has a second substrate with at least one or more deflection devices thereon coupled to the first substrate. At least one or more bonding pads are exposed on the first substrate. The device has a transparent member overlying the second substrate while forming a cavity region to allow the one or more deflection devices to move within a portion of the cavity region to form a sandwich structure including at least a portion of the first substrate, a portion of the second substrate, and a portion of the transparent member.

Abstract: A memory device includes a first metal layer and a first metal oxide layer coupled to the first metal layer. The memory device includes a second metal oxide layer coupled to the first metal oxide layer and a second metal layer coupled to the second metal oxide layer.

Abstract: A resistive memory device is disclosed. The memory device comprises one or mo re metal oxide layers. An oxygen vacancy or ion concentrations of the one or more metal oxide layer is controlled in the formation and the operation of the memory device to provide robust memory operation.

Abstract: Memory devices and methods for providing the memory devices are provided. The memory devices utilize multiple metal oxide layers. The methods for providing the memory devices can include providing a transistor; producing a capacitor that includes metal layers and metal oxide layers; connecting the capacitor to a side of the transistor; and providing a wordline, bitline, and driveline through connection with the transistor or the capacitor.

Abstract: A memory device includes a first metal layer and a first metal oxide layer coupled to the first metal layer. The memory device includes a second metal oxide layer coupled to the first metal oxide layer and a second metal layer coupled to the second metal oxide layer. The formation of the first metal oxide layer has a Gibbs free energy that is lower than the Gibbs free energy for the formation of the second metal oxide layer.

Abstract: Memory devices and methods for providing the memory devices are provided. The memory devices utilize multiple metal oxide layers. The methods for providing the memory devices can include providing a transistor; producing a capacitor that includes metal layers and metal oxide layers; connecting the capacitor to a side of the transistor; and providing a wordline, bitline, and driveline through connection with the transistor or the capacitor.

Abstract: A method for fabricating a micro electromechanical device includes providing a first substrate including control circuitry. The first substrate has a top surface and a bottom surface. The method also includes forming an insulating layer on the top surface of the first substrate, removing a first portion of the insulating layer so as to form a plurality of standoff structures, and bonding a second substrate to the first substrate. The method further includes thinning the second substrate to a predetermined thickness and forming a plurality of trenches in the second substrate. Each of the plurality of trenches extends to the top surface of the first substrate. Moreover, the method includes filling at least a portion of each of the plurality of trenches with a conductive material, forming the micro electromechanical device in the second substrate, and bonding a third substrate to the second substrate.

Abstract: A resonator includes a CMOS substrate having a first electrode and a second electrode. The CMOS substrate is configured to provide one or more control signals to the first electrode. The resonator also includes a resonator structure including a silicon material layer. The resonator structure is coupled to the CMOS substrate and configured to resonate in response to the one or more control signals.

Abstract: Light-absorbing glass frit material is used to seal an opening in a device or a plurality of devices in a batch process. The glass frit material is applied and then irradiated with light having a wavelength absorbed by the glass frit material so that the glass frit ball undergoes a glassy transition and forms a seal. When sealing an opening in a device, the glass frit material may be applied as a spherical ball such that the spherical ball covers the opening. The volume of the spherical ball may be selected to determine the final shape of the seal.

Abstract: A memory device includes a first metal layer and a first metal oxide layer coupled to the first metal layer. The memory device includes a second metal oxide layer coupled to the first metal oxide layer and a second metal layer coupled to the second metal oxide layer. The formation of the first metal oxide layer has a Gibbs free energy that is lower than the Gibbs free energy for the formation of the second metal oxide layer.

Abstract: A MEMS mirror for a laser printing application includes providing a CMOS substrate including a pair of electrodes, and providing a reflecting mirror moveable over the substrate and the electrodes. Voltages applied to the electrodes create an electrostatic force causing an end of the mirror to be attracted to the substrate. A precise position of the mirror can be detected and controlled by sensing a change in capacitance between the mirror ends and the underlying electrodes.

Abstract: A system for hermetically sealing devices includes a substrate, which includes a plurality of individual chips. Each of the chips includes a plurality of devices and each of the chips are arranged in a spatial manner as a first array. The system also includes a transparent member of a predetermined thickness, which includes a plurality of recessed regions arranged in a spatial manner as a second array and each of the recessed regions are bordered by a standoff region. The substrate and the transparent member are aligned in a manner to couple each of the plurality of recessed regions to a respective one of said plurality of chips. Each of the chips within one of the respective recessed regions is hermetically sealed by contacting the standoff region of the transparent member to the plurality of first street regions and second street regions using at least a bonding process to isolate each of the chips within one of the recessed regions.

Abstract: A sensor package has integrated magnetic and acceleration sensor package structures, where a first wafer is bonded to a second wafer with a cavity defined between them. The magnetic sensor is bonded to the bottom of the first wafer and the acceleration sensor is provided within the cavity. Circuitry to drive the accelerometer and interface with the magnetic sensor is provided on the first wafer.

Abstract: A method for fabricating a micro electromechanical device includes providing a first substrate including control circuitry. The first substrate has a top surface and a bottom surface. The method also includes forming an insulating layer on the top surface of the first substrate, removing a first portion of the insulating layer so as to form a plurality of standoff structures, and bonding a second substrate to the first substrate. The method further includes thinning the second substrate to a predetermined thickness and forming a plurality of trenches in the second substrate. Each of the plurality of trenches extends to the top surface of the first substrate. Moreover, the method includes filling at least a portion of each of the plurality of trenches with a conductive material, forming the micro electromechanical device in the second substrate, and bonding a third substrate to the second substrate.