Abstract: A three-wheeled all-terrain vehicle or push chair utilizes an innovative front wheel mount, employing a side-mounted caster mechanism, for improving its pushability and steerability. Because of this approach, lifting is not required to steer the chair, and any size or type and width of wheel can be used. As a result, the invention provides a new class of all-terrain product for the disabled adult market and a rugged, truly off-road runner/jogger/hiker stroller for the young child market.

Abstract: Systems, methods and/or devices are used to enable tracking intermix of writes and un-map commands across power cycles. In one aspect, the method includes (1) receiving, at a storage device, a plurality of commands from a host, the storage device including non-volatile memory, (2) maintaining a log corresponding to write commands and un-map commands from the host, (3) maintaining a mapping table in volatile memory, the mapping table used to translate logical addresses to physical addresses, (4) saving the mapping table, on a scheduled basis that is independent of the un-map commands, to the non-volatile memory of the storage device, (5) saving the log to the non-volatile memory, and (6) upon power up of the storage device, rebuilding the mapping table from the saved mapping table in the non-volatile memory of the storage device and from the saved log in the non-volatile memory of the storage device.

Abstract: A storage controller is provided that contains multiple processors. In some embodiments, the storage controller is coupled to a flash memory module having multiple flash memory groups, each flash memory group corresponding to a distinct flash port in the storage controller, each flash port comprising an associated processor. Each processor handles a portion of one or more host commands, including reads and writes, allowing multiple parallel pipelines to handle one or more host commands simultaneously.

Abstract: A storage controller is provided that contains multiple processors. In some embodiments, the storage controller is coupled to a flash memory module having multiple flash memory groups, each flash memory group corresponding to a distinct flash port in the storage controller, each flash port comprising an associated processor. Each processor handles a portion of one or more host commands, including reads and writes, allowing multiple parallel pipelines to handle one or more host commands simultaneously.

Abstract: Systems, methods and/or devices are used to enable tracking intermix of writes and un-map commands across power cycles. In one aspect, the method includes (1) receiving, at a storage device, a plurality of commands from a host, the storage device including non-volatile memory, (2) maintaining a log corresponding to write commands and un-map commands from the host, (3) maintaining a mapping table in volatile memory, the mapping table used to translate logical addresses to physical addresses, (4) saving the mapping table, on a scheduled basis that is independent of the un-map commands, to the non-volatile memory of the storage device, (5) saving the log to the non-volatile memory, and (6) upon power up of the storage device, rebuilding the mapping table from the saved mapping table in the non-volatile memory of the storage device and from the saved log in the non-volatile memory of the storage device.

Abstract: A storage controller is provided that contains multiple processors. In some embodiments, the storage controller is coupled to a flash memory module having multiple flash memory groups, each flash memory group corresponding to a distinct flash port in the storage controller, each flash port comprising an associated processor. Each processor handles a portion of one or more host commands, including reads and writes, allowing multiple parallel pipelines to handle one or more host commands simultaneously.

Abstract: A storage controller has multiple processors, divided into groups, each of which handles a different stage of a pipelined process of performing host reads and writes. In some embodiments, the storage controller operates with a flash memory module, and includes a first processor group, a second processor group and a third processor group, each having one or more processors for handling a different stage of a pipelined execution of host storage commands. With respect to a first host command, a first processor of the first processor group, a first processor of the second processor group, and a first processor of the third processor group comprise a first pipeline, and with respect to a second host command, a second processor of the first processor group, a second processor of the second processor group, and a second processor of the third processor group comprise a second pipeline.

Abstract: A storage controller is provided that contains multiple processors. In some embodiments, the storage controller is coupled to a flash memory module having multiple flash memory groups, each flash memory group corresponding to a distinct flash port in the storage controller, each flash port comprising an associated processor. Each processor handles a portion of one or more host commands, including reads and writes, allowing multiple parallel pipelines to handle one or more host commands simultaneously.

Abstract: A method of rebuilding metadata in a flash memory controller following a loss of power is provided. The method includes reading logical address information associated with an area of flash memory, and using time stamp information to determine if data stored in the flash memory area are valid.

Abstract: A method for recovering corrupted data stored in persistent memory provides protection against, at least, loss of a single block, loss of a single page, as well as a high number of random retention errors. In some implementations, each data element in a quadrant of the persistent memory is protected by a row check word and a diagonal check word. Each row check word includes a value resulting from a mathematical operation performed on a respective row set comprising a set of data elements and each diagonal check word in the quadrant includes a value resulting from a mathematical operation performed on a respective diagonal set comprising a set of data elements distributed over the banks, blocks and pages in the quadrant so that failure of any one page, block or die in the quadrant does not result in the loss of any data in the quadrant.

Abstract: A storage controller is provided that contains multiple processors. In some embodiments, the storage controller is coupled to a flash memory module having multiple flash memory groups, each flash memory group corresponding to a distinct flash port in the storage controller, each flash port comprising an associated processor. Each processor handles a portion of one or more host commands, including reads and writes, allowing multiple parallel pipelines to handle one or more host commands simultaneously.

Abstract: A storage controller is provided that contains multiple processors. In some embodiments, the storage controller is coupled to a flash memory module having multiple flash memory groups, each flash memory group corresponding to a distinct flash port in the storage controller, each flash port comprising an associated processor. Each processor handles a portion of one or more host commands, including reads and writes, allowing multiple parallel pipelines to handle one or more host commands simultaneously.

Abstract: A storage controller is provided that contains multiple processors. In some embodiments, the storage controller is coupled to a flash memory module having multiple flash memory groups, each flash memory group corresponding to a distinct flash port in the storage controller, each flash port comprising an associated processor. Each processor handles a portion of one or more host commands, including reads and writes, allowing multiple parallel pipelines to handle one or more host commands simultaneously.

Abstract: A controller designed for use with a flash memory storage module, including a crossbar switch designed to connect a plurality of internal processors with various internal resources, including a plurality of internal memories. The memories contain work lists for the processors. In one embodiment, the processors communicate by using the crossbar switch to place tasks on the work lists of other processors.

Abstract: A storage controller containing multiple processors. The processors are divided into groups, each of which handles a different stage of a pipelined process of performing host reads and writes. In one embodiment, the storage controller operates with a flash memory module, and includes multiple parallel pipelines that allow plural host commands to be handled simultaneously.

Abstract: A volatile memory associated with a mass storage controller and a flash memory module. The volatile memory includes a number of tables containing information related to the flash memory storage, including a table storing physical flash memory addresses and a plurality of tables containing metadata.

Abstract: A storage controller connected to a flash memory storage module, the controller and module including multiple sets of buffers. The buffers are part of one or more pipelines through which data is moved between the storage module and one or more hosts.

Abstract: A storage controller is provided that contains multiple processors. In some embodiments, the storage controller is coupled to a flash memory module having multiple flash memory groups, each flash memory group corresponding to a distinct flash port in the storage controller, each flash port comprising an associated processor. Each processor handles a portion of one or more host commands, including reads and writes, allowing multiple parallel pipelines to handle one or more host commands simultaneously.

Abstract: A method of rebuilding metadata in a flash memory controller following a loss of power is provided. The method includes reading logical address information associated with an area of flash memory, and using time stamp information to determine if data stored in the flash memory area are valid.

Abstract: A method of rebuilding metadata in a flash memory controller following a loss of power. The method includes reading logical address information associated with an area of flash memory, and using time stamp information to determine if data stored in the flash memory area is valid.