Abstract: In a storage controller connected to a flash memory module, an execute loop used to carry out tasks related to reading or writing data from the module. The loop includes reading a data structure from a queue and carrying out a task specified by the data structure, unless resources required by the task are not available, in which event the loop moves on to another data structure stored in another queue. Data structures bypassed by the loop are periodically revisited, until all tasks required are completed. Data structures store state information that is updated when tasks are completed.

Abstract: A storage controller is provided that contains multiple processors. In some embodiments, the storage controller is coupled to a flash memory module having multiple flash memory groups, each flash memory group corresponding to a distinct flash port in the storage controller, each flash port comprising an associated processor. Each processor handles a portion of one or more host commands, including reads and writes, allowing multiple parallel pipelines to handle one or more host commands simultaneously.

Abstract: A storage controller has multiple processors, divided into groups, each of which handles a different stage of a pipelined process of performing host reads and writes. In some embodiments, the storage controller operates with a flash memory module, and includes a first processor group, a second processor group and a third processor group, each having one or more processors for handling a different stage of a pipelined execution of host storage commands. With respect to a first host command, a first processor of the first processor group, a first processor of the second processor group, and a first processor of the third processor group comprise a first pipeline, and with respect to a second host command, a second processor of the first processor group, a second processor of the second processor group, and a second processor of the third processor group comprise a second pipeline.

Abstract: A flash memory controller connected to multiple flash memory groups performs independent garbage collection operations in each group. For each group, the controller independently determines the amount of free space and performs garbage collection operations if the amount falls below a threshold.

Abstract: A flash memory controller connected to multiple flash memory groups performs independent garbage collection operations in each group. For each group, the controller independently determines the amount of free space and performs garbage collection operations if the amount falls below a threshold.

Abstract: A patrol function performed in a storage controller connected to a flash memory storage module. The function causes selected areas of the flash storage to be read for purposes of detecting and correcting errors.

Abstract: A flash memory controller connected to multiple flash memory groups performs independent garbage collection operations in each group. For each group, the controller independently determines the amount of free space and performs garbage collection operations if the amount falls below a threshold.

Abstract: Disclosed is a flash memory controller connected to a flash memory module. The pin-out of the flash memory controller combines ready-busy and chip-select signals. In one embodiment, the flash memory module is made up of a set of banks, each consisting of a plurality of devices, with each bank sharing a single chip-select/ready-busy connection to the controller.

Abstract: Disclosed is a mass storage system and method for breaking a host command into a hierarchy of data structures. Different types of data structures are designed to handle different phases of tasks required by the host command, and multiple data structures may be used to handle portions of the host command in parallel, thereby allowing increased performance. The disclosed embodiments include a flash memory controller designed to allow a high degree of pipelining and parallelism.

Abstract: A method of rebuilding metadata in a flash memory controller following a loss of power. The method includes reading logical address information associated with an area of flash memory, and using time stamp information to determine if data stored in the flash memory area is valid.

Abstract: A volatile memory associated with a mass storage controller and a flash memory module. The volatile memory includes a number of tables containing information related to the flash memory storage, including a table storing physical flash memory addresses and a plurality of tables containing metadata.

Abstract: A storage controller connected to a flash memory storage module, the controller and module including multiple sets of buffers. The buffers are part of one or more pipelines through which data is moved between the storage module and one or more hosts.

Abstract: Disclosed is a flash memory controller connected to a flash memory module. The pin-out of the flash memory controller combines ready-busy and chip-select signals. In one embodiment, the flash memory module is made up of a set of banks, each consisting of a plurality of devices, with each bank sharing a single chip-select/ready-busy connection to the controller.

Abstract: A storage controller containing multiple processors. The processors are divided into groups, each of which handles a different stage of a pipelined process of performing host reads and writes. In one embodiment, the storage controller operates with a flash memory module, and includes multiple parallel pipelines that allow plural host commands to be handled simultaneously.

Abstract: Disclosed is a mass storage system and method for breaking a host command into a hierarchy of data structures. Different types of data structures are designed to handle different phases of tasks required by the host command, and multiple data structures may be used to handle portions of the host command in parallel, thereby allowing increased performance. The disclosed embodiments include a flash memory controller designed to allow a high degree of pipelining and parallelism.

Abstract: A flash memory controller connected to multiple flash memory groups performs independent garbage collection operations in each group. For each group, the controller independently determines the amount of free space and performs garbage collection operations if the amount falls below a threshold.

Abstract: A controller designed for use with a flash memory storage module, including a crossbar switch designed to connect a plurality of internal processors with various internal resources, including a plurality of internal memories. The memories contain work lists for the processors. In one embodiment, the processors communicate by using the crossbar switch to place tasks on the work lists of other processors.

Abstract: In a storage controller connected to a flash memory module, an execute loop used to carry out tasks related to reading or writing data from the module. The loop includes reading a data structure from a queue and carrying out a task specified by the data structure, unless resources required by the task are not available, in which event the loop moves on to another data structure stored in another queue. Data structures bypassed by the loop are periodically revisited, until all tasks required are completed. Data structures store state information that is updated when tasks are completed.

Abstract: A patrol function performed in a storage controller connected to a flash memory storage module. The function causes selected areas of the flash storage to be read for purposes of detecting and correcting errors.

Abstract: Methods for controlling and storing data in a cache buffer in a storage apparatus having a nonvolatile memory medium are disclosed. Memory cells are logically divided into a plurality of pages. An open status is registered in a counter for each page that has at least some (and usually all) memory cells available to store new data. A full status is registered in the counter for each page that does not have memory cells that are available to store new data. New data is stored in pages having the open status in the counter. The pages can be weighted according to the read command rate and prioritized for reading and writing purposes.