Abstract: Apparatus and methods are disclosed for nullifying memory store instructions identified in a target field of a nullification instruction. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores configured to fetch and execute a plurality of instruction blocks. One of the cores can include a control unit configured, based at least in part on receiving a nullification instruction, to obtain an instruction identification for a memory access instruction of a plurality of memory access instructions, based on a target field of the nullification instruction. The memory access instruction associated with the instruction identification is nullified. The memory access instruction is in a first instruction block of the plurality of instruction blocks. Based on the nullified memory access instruction, a subsequent memory access instruction from the first instruction block is executed.

Abstract: Systems and methods are disclosed for allocating resources to contexts in block-based processor architectures. In one example of the disclosed technology, a processor is configured to spatially allocate resources between multiple contexts being executed by the processor, including caches, functional units, and register files. In a second example of the disclosed technology, a processor is configured to temporally allocate resources between multiple contexts, for example, on a clock cycle basis, including caches, register files, and branch predictors. Each context is guaranteed access to its allocated resources to avoid starvation from contexts competing for resources of the processor. A results buffer can be used for folding larger instruction blocks into portions that can be mapped to smaller-sized instruction windows. The results buffer stores operand results that can be passed to subsequent portions of an instruction block.

Abstract: Apparatus and methods are disclosed for nullifying memory store instructions and one or more registers identified in a target field of a nullification instruction. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores configured to fetch and execute a plurality of instruction blocks. One of the cores can include a control unit configured, based at least in part on receiving a nullification instruction, to obtain an instruction identification for a memory access instruction of a plurality of memory access instructions and a register identification of at least one of a plurality of registers, based on a first and second target fields of the nullification instruction. The at least one register and the memory access instruction associated with the instruction identification are nullified. Based on the nullified memory access instruction, a subsequent memory access instruction is executed.

Abstract: A server system is provided that includes a plurality of servers, each server including at least one hardware acceleration device and at least one processor communicatively coupled to the hardware acceleration device by an internal data bus and executing a host server instance, the host server instances of the plurality of servers collectively providing a software plane, and the hardware acceleration devices of the plurality of servers collectively providing a hardware acceleration plane that implements a plurality of hardware accelerated services, wherein each hardware acceleration device maintains in memory a data structure that contains load data indicating a load of each of a plurality of target hardware acceleration devices, and wherein a requesting hardware acceleration device routes the request to a target hardware acceleration device that is indicated by the load data in the data structure to have a lower load than other of the target hardware acceleration devices.

Abstract: The present invention extends to methods, systems, and computer program products for reconfiguring an acceleration component among interconnected acceleration components. Aspects of the invention facilitate reconfiguring an acceleration component among interconnected acceleration components using a higher-level software service. A manager or controller isolates an acceleration component by sending a message to one or more neighbor acceleration components instructing the one or more neighbor acceleration components to stop accepting communication from the acceleration component. The manager or controller can then shut down an application layer at the acceleration component for at least partial reconfiguration and closes input/output (I/O) portions. After reconfiguration completes, communication between the acceleration component and the one or more neighbor acceleration components can resume.

Abstract: A non-contacting inductive interconnect of a three-dimensional integrated circuit includes a first silicon substrate having a first inductive loop. A first layer of high permeability material is deposited on the first silicon substrate that has the first inductive loop forming a first high permeability structure. The circuit further includes a second silicon substrate having a second inductive loop. A magnetic coupling is formed between the first inductive loop and the second inductive loop. The first high permeability structure can enhance the magnetic coupling between the first inductive loop and the second inductive loop. In some embodiments, a second layer of the high permeability material is deposited on the second silicon substrate that has the second inductive loop forming a second high permeability structure. The first high permeability structure and the second high permeability structure can form a magnetic circuit coupling the first inductive loop and the second inductive loop.

Abstract: Aspects extend to methods, systems, and computer program products for locally restoring functionality at acceleration components. A role can be locally restored at an acceleration component when an error is self-detected at the acceleration component (e.g., by local monitoring logic). Locally restoring a role can include resetting internal state (application logic) of the acceleration component providing the role. Self-detection of errors and local restoration of a role is less resource intensive and more efficient than using external components (e.g., high-level services) to restore functionality at an acceleration component and/or to reset an entire graph. Monitoring logic at multiple acceleration components can locally reset roles in parallel to restore legitimate behavior of a graph.

Abstract: A processor core in an instruction block-based microarchitecture utilizes instruction blocks having headers that include an index to a size table that may be expressed using one of memory, register, logic, or code stream. A control unit in the processor core determines how many instructions to fetch for a current instruction block for mapping into an instruction window based on the block size that is indicated from the size table. As instruction block sizes are often unevenly distributed for a given program, utilization of the size table enables more flexibility in matching instruction blocks to the sizes of available slots in the instruction window as compared to arrangements in which instruction blocks have a fixed sized or are sized with less granularity. Such flexibility may enable denser instruction packing which increases overall processing efficiency by reducing the number of nops (no operations, such as null functions) in a given instruction block.

Abstract: A processor core in an instruction block-based microarchitecture includes a control unit that explicitly tracks instruction block state including age or priority for current blocks that have been fetched from an instruction cache. Tracked instruction blocks are maintained in an age-ordered or priority-ordered list. When an instruction block is identified by the control unit for commitment, the list is checked for a match and a matching instruction block can be refreshed without re-fetching from the instruction cache. If a match is not found, an instruction block can be committed and replaced based on either age or priority. Such instruction state tracking typically consumes little overhead and enables instruction blocks to be reused and mispredicted instructions to be skipped to increase processor core efficiency.

Abstract: Systems and methods of a personal daemon, executing as a background process on a mobile computing device, for providing personal assistant to an associated user is presented. While the personal daemon maintains personal information corresponding to the associated user, the personal daemon is configured to not share the personal information of the associated user with any other entity other than the associated user except under conditions of rules established by the associated user. The personal daemon monitors and analyzes the actions of the associated user to determine additional personal information of the associated user. Additionally, upon receiving one or more notices of events from a plurality of sensors associated with the mobile computing device, the personal daemon executes a personal assistance action on behalf of the associated user.

Abstract: A data processing system is described herein that includes two or more software-driven host components. The two or more host components collectively provide a software plane. The data processing system also includes two or more hardware acceleration components (such as FPGA devices) that collectively provide a hardware acceleration plane. A common physical network allows the host components to communicate with each other, and which also allows the hardware acceleration components to communicate with each other. Further, the hardware acceleration components in the hardware acceleration plane include functionality that enables them to communicate with each other in a transparent manner without assistance from the software plane.

Abstract: Aspects extend to methods, systems, and computer program products for (re)configuring acceleration components over a network. (Re)configuration can be implemented for any of a variety of reasons, including to address an error in functionality at the acceleration component or to update functionality at the acceleration component. During (re)configuration, connectivity can be maintained for any other functionality at the acceleration component untouched by the (re)configuration. Network (re)configuration of acceleration components facilitates management of acceleration components and accelerated services from a centralized service. Network (re)configuration of acceleration components also relieves host components from having to store (potentially diverse and numerous) image files.

Abstract: Functional units disposed in one or more processor cores are communicatively coupled using both a shared bypass network and a switched network. The shared bypass network enables the functional units to be operated conventionally for general processing while the switched network enables specialized processing in which the functional units are configured as a spatial array. In the spatial array configuration, operands produced by one functional unit can only be sent to a subset of functional units to which dependent instructions have been mapped a priori. The functional units may be dynamically reconfigured at runtime to toggle between operating in the general configuration and operating as the spatial array. Information to control the toggling between operating configurations may be provided in instructions received by the functional units.

Abstract: A data processing system is described herein that includes two or more software-driven host components. The two or more host components collectively provide a software plane. The data processing system also includes two or more hardware acceleration components (such as FPGA devices) that collectively provide a hardware acceleration plane. A common physical network allows the host components to communicate with each other, and which also allows the hardware acceleration components to communicate with each other. Further, the hardware acceleration components in the hardware acceleration plane include functionality that enables them to communicate with each other in a transparent manner without assistance from the software plane.

Abstract: Techniques are described for validating stateful app links. Validation can be performed when stateful app links are created, activated, shared, or at other times. Validation can be performed to determine whether a stateful app link has a dependency on a resource external to the mobile application. Validation can also be performed to detect other issues, such as security issues, privacy issues, or other issues.

Abstract: Techniques are described for dynamically generating stateful app links. For example, page launcher events can be intercepted during user interaction with a mobile application. During the interaction, a request can be received to dynamically generate a stateful app link to a current page of the mobile application. In response to the request, a stateful app link to the current page can be created. The stateful app link can then be output. When the stateful app link is activated later, it returns to the current page of the mobile application. In some implementations, user interface events are also captured and used when creating the stateful app link.

Abstract: Systems and methods for providing client-side integration of apps and services is provided. An integration framework execution upon a computing device provides integration of various apps, applications, services, sensors and the like. Upon receiving a request for a service, the integration framework accesses a registry of a plurality of services of a respective plurality of providers registered with the integration framework. Each of the services is registered with the integration framework is associated with a trust level of a hierarchy of trust levels. The integration framework iteratively searches the registry for a provider of the requested service according to the hierarchy of trust levels, beginning with the most trusted level of the trust levels to the less trusted trust level until a provider of the requested service is found or until all levels of the hierarchy are searched without finding a provider of the requested service.

Abstract: Systems and methods of a personal daemon, executing as a background process on a mobile computing device, for providing personal assistant to an associated user is presented. Also executing on the mobile computing device is a scheduling manager. The personal daemon executes one or more personal assistance actions on behalf of the associated user. The scheduling manager responds to events in support of the personal daemon. More particularly, in response to receiving an event the scheduling manager determines a set of apps that are responsive to the received event and from that set of apps, identifies at least a first subset of apps for execution on the mobile computing device. The scheduling manager receives feedback information regarding the usefulness of the executed apps of the first subset of apps and updates the associated score of each of the apps of the first subset of apps.

Abstract: Systems and methods are disclosed for initiating a monitoring session between a user device and a pet monitoring system including a base station and a plurality of monitoring devices. The base station receives a request to monitor the pet from the user device, activates the plurality of monitoring devices, receives data from the plurality of monitoring devices, locates the pet based on the received data from the plurality of monitoring devices, selects a selected monitoring device of the plurality of monitoring devices based upon at least one of the data from the plurality of monitoring devices and the location of the pet, and transmits the data from the selected monitoring device to the user device.

Abstract: A processor core in an instruction block-based microarchitecture includes a control unit that allocates instructions into an instruction window in bulk by fetching blocks of instructions and associated resources including control bits and operands at once. Such bulk allocation supports increased efficiency in processor core operations by enabling consistent management and policy implementation across all the instructions in the block during execution. For example, when an instruction block branches back on itself, it may be reused in a refresh process rather than being re-fetched from the instruction cache. As all of the resources for that instruction block are in one place, the instructions can remain in place and only valid bits need to be cleared. Bulk allocation also facilitates operand sharing by instructions in a block and explicit messaging among instructions.