Abstract: Technology related to prefetching data associated with predicated stores of programs in block-based processor architectures is disclosed. In one example of the disclosed technology, a processor includes a block-based processor core for executing an instruction block comprising a plurality of instructions. The block-based processor core includes decode logic and prefetch logic. The decode logic is configured to detect a predicated store instruction of the instruction block. The prefetch logic is configured to calculate a target address of the predicated store instruction and initiate a memory operation associated with the calculated target address before a predicate of the predicated store instruction is calculated.

Abstract: Apparatus and methods are disclosed for decoding targets from an instruction and transmitting data to those targets in accordance with a current instruction. Multimodal target hardware is used in conjunction with one or more of the routers so as to route data to an appropriate target. The data can be one or more operands or a predicate and the targets can include operand buffers, broadcast channels, and general registers. In this way, operands, for example, can be directed for use with multiple subsequent instructions, and there are multiple modes for distributing the operands to the multiple instructions.

Abstract: Distinct system registers for logical processors are disclosed. In one example of the disclosed technology, a processor includes a plurality of block-based physical processor cores for executing a program comprising a plurality of instruction blocks. The processor also includes a thread scheduler configured to schedule a thread of the program for execution, the thread using the one or more instruction blocks. The processor further includes at least one system register. The at least one system register stores data indicating a number and placement of the plurality of physical processor cores to form a logical processor. The logical processor executes the scheduled thread. The logical processor is configured to execute the thread in a continuous instruction window.

Abstract: Apparatus and methods are disclosed for nullifying memory store instructions and one or more registers identified in a target field of a nullification instruction. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores configured to fetch and execute a plurality of instruction blocks. One of the cores can include a control unit configured, based at least in part on receiving a nullification instruction, to obtain an instruction identification for a memory access instruction of a plurality of memory access instructions and a register identification of at least one of a plurality of registers, based on a first and second target fields of the nullification instruction. The at least one register and the memory access instruction associated with the instruction identification are nullified. Based on the nullified memory access instruction, a subsequent memory access instruction is executed.

Abstract: Apparatus and methods are disclosed for controlling execution of memory access instructions in a block-based processor architecture using a hardware structure that generates a relative ordering of memory access instruction in an instruction block. In one example of the disclosed technology, a method of executing an instruction block having a plurality of memory load and/or memory store instructions includes decoding an instruction block encoding a plurality of memory access instructions and generating data indicating a relative order for executing the memory access instructions in the instruction block and scheduling operation of a portion of the instruction block based at least in part on the relative order data. In some examples, a store vector data register can store the generated relative ordering data for use in subsequent instances of the instruction block.

Abstract: Apparatus and methods are disclosed for nullifying one or more registers identified in a target field of a nullification instruction. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores configured to fetch and execute a plurality of instruction blocks. One of the cores can include a control unit configured, based at least in part on receiving a nullification instruction, to obtain a register identification of at least one of a plurality of registers, based on a target field of the nullification instruction. A write to the at least one register associated with the register identification is nullified. The nullification instruction is in a first instruction block of the plurality of instruction blocks. Based on the nullified write to the at least one register, a subsequent instruction is executed from a second, different instruction block.

Abstract: Apparatus and methods are disclosed for generating and using block branch metadata in block-based processor architectures. In one example of the disclosed technology, a block-based processor is configured to dynamically generate metadata representing control flow, exit points, and control flow probabilities for an instruction block while decoding and executing the block. The metadata can be used with subsequent invocations of the instruction block for branch and memory dependence predictions. In some examples, an incomplete portion of a control flow representation is generated for a number of predicated instructions and stored in a memory or storage device for enhancing prediction and prefetch for subsequent invocations of an instruction block.

Abstract: Technology related to prefetching data associated with predicated loads of programs in block-based processor architectures is disclosed. In one example of the disclosed technology, a processor includes a block-based processor core for executing an instruction block comprising a plurality of instructions. The block-based processor core includes decode logic and prefetch logic. The decode logic is configured to detect a predicated load instruction of the instruction block. The prefetch logic is configured to calculate a target address of the predicated load instruction and issue a prefetch request to a memory hierarchy of the processor for data at the calculated target address.

Abstract: Systems, apparatuses, and methods related to a block-based processor core topology register are disclosed. In one example of the disclosed technology, a processor can include a plurality of block-based processor cores for executing a program including a plurality of instruction blocks. A respective block-based processor core can include a sharable resource and a programmable composition topology register. The programmable composition topology register can be used to assign a group of the physical processor cores that share the sharable resource.

Abstract: Apparatus and methods are disclosed for controlling instruction flow in block-based processor architectures. In one example of the disclosed technology, an instruction block address register stores an index address to a memory storing a plurality of instructions for an instruction block, the indexed address being inaccessible when the processor is in one or more unprivileged operational modes, one or more execution units configured to execute instructions for the instruction block, and a control unit configured to fetch and decode two or more of the plurality of instructions from the memory based on the indexed address.

Abstract: A method of lossless data compression includes receiving a set of parallel data strings; determining compression hash values for each of the parallel data strings; determining bit matches among portions of each of the parallel data strings based, at least in part, on the compression hash values; selecting among literals and the bit matches for each of the parallel data strings; and applying Huffman encoding to the selected literals or the selected bit matches.

Abstract: Systems and methods are described relating to determining a specified time period of non-movement in a mobile device and presenting an indication of location of the mobile device at least partially based on the specified time period of non-movement. Additionally, systems and methods are described relating to means for determining a specified time period of non-movement in a mobile device and means for presenting an indication of location of the mobile device at least partially based on the specified time period of non-movement.

Abstract: Embodiments of the virtual machine power metering system and method measure the power consumption of individual virtual machines. Power meter measurements for a physical host server are converted into individual virtual machine power meters that measure the power consumption of each individual virtual machine residing on the host server. The virtual machine power consumption is computed by generating a power model using the total power consumption of the host server and resource utilization for a virtual machine. Optimal power model coefficients are computed using the power model. The energy used by the virtual machine is computed using one of two embodiments. Embodiments of the system and method also can be used to obtain the power consumption for a specific activity (such as a service, request, or search query). In addition, the virtual machine power metering can be used for virtual machine power capping to allow power oversubscription in virtualized environments.

Abstract: Systems and methods for providing client-side integration of apps and services is provided. An integration framework execution upon a computing device provides integration of various apps, applications, services, sensors and the like. Upon receiving a request for a service, the integration framework accesses a registry of a plurality of services of a respective plurality of providers registered with the integration framework. Each of the services is registered with the integration framework is associated with a trust level of a hierarchy of trust levels. The integration framework iteratively searches the registry for a provider of the requested service according to the hierarchy of trust levels, beginning with the most trusted level of the trust levels to the less trusted trust level until a provider of the requested service is found or until all levels of the hierarchy are searched without finding a provider of the requested service.

Abstract: Systems and methods of a personal daemon, executing as a background process on a mobile computing device, for providing personal assistant to an associated user is presented. While the personal daemon maintains personal information corresponding to the associated user, the personal daemon is configured to not share the personal information of the associated user with any other entity other than the associated user except under conditions of rules established by the associated user. The personal daemon monitors and analyzes the actions of the associated user to determine additional personal information of the associated user. Additionally, upon receiving one or more notices of events from a plurality of sensors associated with the mobile computing device, the personal daemon executes a personal assistance action on behalf of the associated user.

Abstract: A processor is described herein that is configured to switch between a first instruction issue mode of the processor and a second instruction issue mode of the processor based at least in part on a characteristic associated with a plurality of instructions. The first instruction issue mode and the second instruction issue mode are associated with different energy consumption characteristics. Also, the first instruction issue mode may be an out-of-order instruction issue mode and the second instruction issue mode may be an in-order instruction issue mode.

Abstract: A processor core in an instruction block-based microarchitecture includes a control unit that explicitly tracks instruction block state including age or priority for current blocks that have been fetched from an instruction cache. Tracked instruction blocks are maintained in an age-ordered or priority-ordered list. When an instruction block is identified by the control unit for commitment, the list is checked for a match and a matching instruction block can be refreshed without re-fetching from the instruction cache. If a match is not found, an instruction block can be committed and replaced based on either age or priority. Such instruction state tracking typically consumes little overhead and enables instruction blocks to be reused and mispredicted instructions to be skipped to increase processor core efficiency.

Abstract: A method is provided for processing on an acceleration component a deep neural network. The method includes configuring the acceleration component to perform forward propagation and backpropagation stages of the deep neural network. The acceleration component includes an acceleration component die and a memory stack disposed in an integrated circuit package. The memory stack has a memory bandwidth greater than about 50 GB/sec and a power efficiency of greater than about 20 MB/sec/mW.

Abstract: A server unit component is provided that includes a host component including a CPU, and an acceleration component coupled to the host component. The acceleration component includes an acceleration component die and a memory stack. The acceleration component die and the memory stack are disposed in an integrated circuit package. The memory stack has a memory bandwidth greater than about 50 GB/sec and a power efficiency of greater than about 20 MB/sec/mW.

Abstract: Aspects extend to methods, systems, and computer program products for allocating acceleration component functionality for supporting services. A service manager uses a finite number of acceleration components to accelerate services. Acceleration components can be allocated in a manner that balances load in a hardware acceleration plane, minimizes role switching, and adapts to demand changes. When role switching is appropriate, less extensive mechanisms (e.g., based on configuration data versus image files) can be used to switch roles to the extent possible.