Patents by Inventor Ebenezer E. Eshun
Ebenezer E. Eshun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7768055Abstract: Passive components are formed in the back end by using the same deposition process and materials as in the rest of the back end. Resistors are formed by connecting in series individual structures on the nth, (n+1)th, etc levels of the back end. Capacitors are formed by constructing a set of vertical capacitor plates from a plurality of levels in the back end, the plates being formed by connecting electrodes on two or more levels of the back end by vertical connection members.Type: GrantFiled: November 30, 2005Date of Patent: August 3, 2010Assignee: International Business Machines CorporationInventors: Anil K. Chinthakindi, Douglas D. Coolbaugh, Ebenezer E. Eshun, Zhong-Xiang He, Jeffrey B. Johnson, Jonghae Kim, Jean-Oliver Plouchart, Anthony K. Stamper
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Publication number: 20100149723Abstract: The invention is directed to an improved capacitor that reduces edge defects and prevents yield failures. A first embodiment of the invention comprises a protective layer adjacent an interface of a conductive layer with the insulator, while the second embodiment of the invention comprises a protective layer on an insulator which is on a conductive layer.Type: ApplicationFiled: February 17, 2010Publication date: June 17, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: EBENEZER E. ESHUN, RONALD J. BOLAM, DOUGLAS D. COOLBAUGH, KEITH E. DOWNES, NATALIE B. FEILCHENFELD, ZHONG-XIANG HE
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Patent number: 7728372Abstract: The invention is directed to an improved capacitor that reduces edge defects and prevents yield failures. A first embodiment of the invention comprises a protective layer adjacent an interface of a conductive layer with the insulator, while the second embodiment of the invention comprises a protective layer on an insulator which is on a conductive layer.Type: GrantFiled: May 10, 2006Date of Patent: June 1, 2010Assignee: International Business Machines CorporationInventors: Ebenezer E. Eshun, Ronald J. Bolam, Douglas D. Coolbaugh, Keith E. Downes, Natalie B. Feilchenfeld, Zhong-Xiang He
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Patent number: 7691717Abstract: A polysilicon containing resistor includes: (1) a p dopant selected from the group consisting of boron and boron difluoride; and (2) an n dopant selected from the group consisting of arsenic and phosphorus. Each of the p dopant and the n dopant has a dopant concentration from about 1e18 to about 1e21 dopant atoms per cubic centimeter. A method for forming the polysilicon resistor uses corresponding implant doses from about 1e14 to about 1e16 dopant ions per square centimeter. The p dopant and the n dopant may be provided simultaneously or sequentially. The method provides certain polysilicon resistors with a sheet resistance percentage standard deviation of less than about 1.5%, for a polysilicon resistor having a sheet resistance from about 100 to about 5000 ohms per square.Type: GrantFiled: July 19, 2006Date of Patent: April 6, 2010Assignee: International Business Machines CorporationInventors: Anil K. Chinthakindi, Douglas D. Coolbaugh, Ebenezer E. Eshun, John E. Florkey, Robert M. Rassel, Kunal Vaed
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Patent number: 7687867Abstract: A method to integrate MIM capacitors into conductive interconnect levels, with low cost impact, and high yield, reliability and performance than existing integration methods is provided. This is accomplished by recessing a prior level dielectric for MIM capacitor level alignment followed by deposition and patterning of the MIM capacitor films. Specifically, the method includes providing a substrate including a wiring level, the wiring level comprising at least one conductive interconnect formed in a dielectric layer; selectively removing a portion of the dielectric layer to recess the dielectric layer below an upper surface of the at least one conductive interconnect; forming a dielectric stack upon the at least one conductive interconnect and the recessed dielectric layer; and forming a metal-insulator-metal (MIM) capacitor on the dielectric stack. The MIM capacitor includes a bottom plate electrode, a dielectric and a top plate electrode.Type: GrantFiled: August 28, 2007Date of Patent: March 30, 2010Assignee: International Business Machines CorporationInventors: Douglas D. Coolbaugh, Ebenezer E. Eshun, Zhong-Xiang He, William J. Murphy, Vidhya Ramachandran
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Patent number: 7670921Abstract: A method of forming a metal-insulator-metal (MIM) capacitor includes forming a first planar dielectric layer with a first metallization layer therein; forming a first passivation layer on top thereof; forming a planar conductive layer above the first passivation layer; patterning and selectively removing the conductive layer up to the first passivation layer in designated areas to form a set of conductive features; patterning and conformally coating the set of conductive features and the exposed first passivation layer with a high strength dielectric coating; disposing a second dielectric layer above the first passivation layer and enclosing the set of conductive features; patterning and selectively removing portions of the second substrate to form channels and trenches; performing a dual-Damascene process to form a second metallization layer in the trenches and channels and to form an upper conductive surface above the high strength dielectric coating.Type: GrantFiled: December 28, 2006Date of Patent: March 2, 2010Assignee: International Business Machines CorporationInventors: Anil K. Chinthakindi, Douglas D. Coolbaugh, Timothy J. Dalton, Ebenezer E. Eshun, Jeffrey P. Gambino, Anthony K. Stamper, Richard P. Volant
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Patent number: 7662722Abstract: A method is provided for fabricating a microelectronic chip which includes a passive device such, as an inductor, overlying an air gap. In such method, a plurality of front-end-of-line (“FEOL”) devices are formed in a semiconductor region of the microelectronic chip, and a plurality of stacked interlevel dielectric (“ILD”) layers are formed to overlie the plurality of FEOL devices, the plurality of stacked ILD layers including a first ILD layer and a second ILD layer, where the second ILD layer is resistant to attack by a first etchant which attacks the first ILD layer. A passive device is formed to overlie at least the first ILD layer. Using the first etchant, a portion of the first ILD layer in registration with the passive device is removed to form an air gap which underlies the passive device in registration with the passive device.Type: GrantFiled: January 24, 2007Date of Patent: February 16, 2010Assignee: International Business Machines CorporationInventors: Anthony K. Stamper, Anil K. Chinthakindi, Douglas D. Coolbaugh, Timothy J. Dalton, Daniel C. Edelstein, Ebenezer E. Eshun, Jeffrey P. Gambino, William J. Murphy, Kunal Vaed
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Patent number: 7659176Abstract: Tunable TCR resistors incorporated into integrated circuits and a method fabricating the tunable TCR resistors. The tunable TCR resistors including two or more resistors of two or more different materials having opposite polarity and different magnitude TCRs, the same polarity and different magnitude TCRs or having opposite polarity and about the same TCRs.Type: GrantFiled: January 26, 2007Date of Patent: February 9, 2010Assignee: International Business Machines CorporationInventors: Douglas D. Coolbaugh, Ebenezer E. Eshun, Richard J. Rassel, Robert M. Rassel
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Patent number: 7645675Abstract: A parallel plate capacitor formed in the back end of an integrated circuit employs conductive capacitor plates that are formed simultaneously with the other interconnects on that level of the back end (having the same material, thickness, etc). The capacitor plates are set into the interlevel dielectric using the same process as the other interconnects on that level of the back end (preferably dual damascene). Some versions of the capacitors have perforations in the plates and vertical conductive members connecting all plates of the same polarity, thereby increasing reliability, saving space and increasing the capacitive density compared with solid plates.Type: GrantFiled: January 13, 2006Date of Patent: January 12, 2010Assignee: International Business Machines CorporationInventors: Douglas D. Coolbaugh, Hanyi Ding, Ebenezer E. Eshun, Michael D. Gordon, Zhong-Xiang He, Anthony K. Stamper
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Publication number: 20090283840Abstract: A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device located and formed upon an active region of a semiconductor substrate and at least one of a fuse structure, an anti-fuse structure and a resistor structure located and formed at least in part simultaneously upon an isolation region laterally separated from the active region within the semiconductor substrate. The field effect device includes a gate dielectric comprising a high dielectric constant dielectric material and a gate electrode comprising a metal material. The at least one of the fuse structure, anti-fuse structure and resistor structure includes a pad dielectric comprising the same material as the gate dielectric, and optionally, also a fuse, anti-fuse or resistor that may comprise the same metal material as the gate electrode.Type: ApplicationFiled: May 13, 2008Publication date: November 19, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Douglas D. Coolbaugh, Ebenezer E. Eshun, Ephrem G. Gebreselasie, Zhong-Xiang He, Herbert Lei Ho, Deok-kee Kim, Chandrasekharan Kothandaraman, Dan Moy, Robert Mark Rassel, John Matthew Safran, Kenneth Jay Stein, Norman Whitelaw Robson, Ping-Chuan Wang, Hongwen Yan
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Publication number: 20090253239Abstract: A method for fabricating a low-value resistor such as a ballast resistor for bipolar junction transistors. The resistor may be fabricated using layers of appropriate sheet resistance so as to achieve low resistance values in a compact layout. The method may rely on layers already provided by a conventional CMOS process flow, such as contact plugs and fully silicided (FUSI) metal gates.Type: ApplicationFiled: April 3, 2008Publication date: October 8, 2009Applicant: International Business Machines CorporationInventors: Douglas D. Coolbaugh, Ebenezer E. Eshun, Zhong-Xiang He, Robert M. Rassel, Kimball M. Watson
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Patent number: 7585722Abstract: The invention is directed to an integrated circuit comb capacitor with capacitor electrodes that have an increased capacitance between neighboring capacitor electrodes as compared with other interconnects and via contacts formed in the same metal wiring level and at the same pitches. The invention achieves a capacitor that minimizes capacitance tolerance and preserves symmetry in parasitic electrode-substrate capacitive coupling, without adversely affecting other interconnects and via contacts formed in the same wiring level, through the use of, at most, one additional noncritical, photomask.Type: GrantFiled: January 10, 2006Date of Patent: September 8, 2009Assignee: International Business Machines CorporationInventors: Daniel C. Edelstein, Anil K. Chinthakindi, Timothy J. Dalton, Ebenezer E. Eshun, Jeffrey P. Gambino, Sarah L. Lane, Anthony K. Stamper
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Publication number: 20090155993Abstract: Terminal pads and methods of fabricating terminal pads. The methods including forming a conductive diffusion barrier under a conductive pad in or overlapped by a passivation layer comprised of multiple dielectric layers including diffusion barrier layers. The methods including forming the terminal pads subtractively or by a damascene process.Type: ApplicationFiled: January 6, 2009Publication date: June 18, 2009Inventors: Douglas D. Coolbaugh, Daniel C. Edelstein, Ebenezer E. Eshun, Zhong-Xiang He, Robert M. Rassel, Anthony K. Stamper
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Patent number: 7528048Abstract: Resistors that avoid the problems of miniaturization of semiconductor devices and a related method are disclosed. In one embodiment, a resistor includes a planar resistor material that extends vertically within at least one metal layer of a semiconductor device. In another embodiment, a resistor includes a resistor material layer extending between a first bond pad and a second bond pad of a semiconductor device. The two embodiments can be used alone or together. A related method for generating the resistors is also disclosed.Type: GrantFiled: December 12, 2007Date of Patent: May 5, 2009Assignee: International Business Machines CorporationInventors: Douglas D. Coolbaugh, Timothy J. Dalton, Daniel C. Edelstein, Ebenezer E. Eshun, Jeffrey P. Gambino, Kevin S. Petrarca, Anthony K. Stamper, Richard P. Volant
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Patent number: 7511940Abstract: Disclosed is a method of fabricating a metal-insulator-metal (MIM) capacitor. In this method, a dielectric layer is formed above a lower conductor layer and an upper conductor layer is formed above the dielectric layer. The invention then forms an etch stop layer above the upper conductor layer and the dielectric layer, and forms a hardmask (silicon oxide hardmask, a silicon nitride hardmask, etc.) over the etch stop layer. Next, a photoresist is patterned above the hardmask, which allows the hardmask, the etch stop layer, the dielectric layer, and the lower conductor layer to be etched through the photoresist.Type: GrantFiled: August 15, 2007Date of Patent: March 31, 2009Assignee: International Business Machines CorporationInventors: Douglas D. Coolbaugh, Ebenezer E. Eshun, Natalie B. Feilchenfeld, Michael L. Gautsch, Zhong-Xiang He, Matthew D. Moon, Vidhya Ramachandran, Barbara Waterhouse
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Publication number: 20090065898Abstract: In the course of forming a resistor in the back end of an integrated circuit, an intermediate dielectric layer is deposited and a trench etched through it and into a lower dielectric layer by a controllable amount, so that the top of a resistor layer deposited in the trench is close in height to the top of the lower dielectric layer; the trench is filled and the resistor layer outside the trench is removed, after which a second dielectric layer is deposited. Vias passing through the second dielectric layer to contact the resistor then have the same depth as vias contacting metal interconnects in the lower dielectric layer. A tri-layer resistor structure is employed in which the resistive film is sandwiched between two protective layers that block diffusion between the resistor and BEOL ILD layers.Type: ApplicationFiled: November 17, 2008Publication date: March 12, 2009Inventors: Anil K. Chinthakindi, Douglas D. Coolbaugh, John M. Cotte, Ebenezer E. Eshun, Zhong-Xiang He, Anthony K. Stamper, Eric J. White
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Patent number: 7494912Abstract: Terminal pads and methods of fabricating terminal pads. The methods including forming a conductive diffusion barrier under a conductive pad in or overlapped by a passivation layer comprised of multiple dielectric layers including diffusion barrier layers. The methods including forming the terminal pads subtractively or by a damascene process.Type: GrantFiled: December 11, 2007Date of Patent: February 24, 2009Assignee: International Business Machines CorporationInventors: Douglas D. Coolbaugh, Daniel C. Edelstein, Ebenezer E. Eshun, Zhong-Xiang He, Robert M. Rassel, Anthony K. Stamper
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Patent number: 7488643Abstract: A MIM capacitor device and method of making the device. The device includes an upper plate comprising one or more electrically conductive layers, the upper plate having a top surface, a bottom surface and sidewalls; a spreader plate comprising one or more electrically conductive layers, the spreader plate having a top surface, a bottom surface and sidewalls; and a dielectric block comprising one or more dielectric layers the dielectric block having a top surface, a bottom surface and sidewalls, the top surface of the dielectric block in physical contact with the bottom surface of the upper plate, the bottom surface of the dielectric block over the top surface of the spreader plate, the sidewalls of the upper plate and the dielectric block essentially co-planer.Type: GrantFiled: June 21, 2006Date of Patent: February 10, 2009Assignee: International Business Machines CorporationInventors: Douglas Duane Coolbaugh, Ebenezer E. Eshun, Zhong-Xiang He, Robert Mark Rassel
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Patent number: 7485540Abstract: In the course of forming a resistor in the back end of an integrated circuit, an intermediate dielectric layer is deposited and a trench etched through it and into a lower dielectric layer by a controllable amount, so that the top of a resistor layer deposited in the trench is close in height to the top of the lower dielectric layer; the trench is filled and the resistor layer outside the trench is removed, after which a second dielectric layer is deposited. Vias passing through the second dielectric layer to contact the resistor then have the same depth as vias contacting metal interconnects in the lower dielectric layer. A tri-layer resistor structure is employed in which the resistive film is sandwiched between two protective layers that block diffusion between the resistor and BEOL ILD layers.Type: GrantFiled: August 18, 2005Date of Patent: February 3, 2009Assignee: International Business Machines CorporationInventors: Anil K. Chinthakindi, Douglas D. Coolbaugh, John M. Cotte, Ebenezer E. Eshun, Zhong-Xiang He, Anthony K. Stamper, Eric J. White
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Publication number: 20090019414Abstract: A resistor device structure and method of manufacture therefore, wherein the resistor device structure invention includes a plurality of alternating conductive film and insulative film layers, at least two of the conductive film layers being electrically connected in parallel to provide for high current flow through the resistor device at high frequencies with increased temperature and mechanical stability. The alternating conductive film and insulative film layers may be of a planar or non-planar geometric spatial orientation. The alternating conductive film and insulative film layers may include lateral and vertical portions designed to enable a uniform current density flow within the structure itself through a self-ballasting effect within the physical resistor.Type: ApplicationFiled: September 19, 2008Publication date: January 15, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ebenezer E. Eshun, Steven H. Voldman