Abstract: An apparatus and method for testing sense amplifier threshold voltages on an integrated circuit includes one or more sense amplifier modules each including a number of sense amplifier circuits, a voltage generator unit, and detection logic. The voltage generator unit may select a differential voltage to supply to at least some of the sense amplifier circuits, and each sense amplifier circuit may be configured to generate an output value that is dependent upon the applied differential voltage in response to receiving an enable signal. The detection logic may detect and capture an output value of each of the sense amplifier circuits. In one implementation, the voltage generator unit may iteratively select a different differential voltage in response to a control input. Accordingly, the detection logic may capture the output value of the sense amplifiers after each change in differential voltage.

Abstract: A synchronizer circuit for transferring data from a source clock domain to a target clock domain. A first latch in the target clock domain may capture a data value corresponding to current data received from the source clock domain. Under certain conditions, the first latch may enter into a metastable, or undefined logic state. A second latch may remain stable, and store a previous value corresponding to data that has most recently been transferred from the source clock domain to the target clock domain. The respective values output by the two latches may be compared by a detection circuit, and a value derived from the output value of the first latch and corresponding to the current data may be written to an output latch if the current data differs from the stored previous value. The detection circuit may also provide a defined logical value to the output latch even if the first latch is in a metastable state.

Abstract: An apparatus and method for testing driver write-ability strength on an integrated circuit includes one or more drive detection units each including a number of drivers. At least some of the drivers may have a different drive strength and each may drive a voltage onto a respective driver output line. Each drive detection unit may include a number of keeper circuits, each coupled to a separate output line and configured to retain a given voltage on the output line to which it is coupled. Each detection unit may also include a number of detection circuits coupled to detect the drive voltage on each of the output lines. In one implementation, the drive voltage appearing at the output line of each driver may be indicative of that the driver was able to overdrive the voltage being retained on the output line to which it is coupled by the respective keeper circuits.

Abstract: A number of scan flops clocked by a master clock may be used to constructing a scan chain to perform scan tests. During a scan test, data appearing at the regular data input of each scan flop may be written into a master latch of the scan flop during a time period when the scan control signal is in a state corresponding to a capture cycle. A slave latch in each scan flop may latch a value appearing at the regular data input of the scan flop according to a narrow pulse triggered by the rising edge of the master clock when the scan control signal is in the state corresponding to the capture cycle. The slave latch may latch the data provided by the master latch according to a wide pulse triggered by the rising edge of the master clock when the scan control signal is in a state corresponding to a shift cycle. This may permit toggling the scan control signal during either a high phase or a low phase of the master clock, and may also enable testing the pulse functionality of each scan flop.

Abstract: A synchronizer circuit for transferring data from a source clock domain to a target clock domain. A first latch in the target clock domain may capture a data value corresponding to current data received from the source clock domain. Under certain conditions, the first latch may enter into a metastable, or undefined logic state. A second latch may remain stable, and store a previous value corresponding to data that has most recently been transferred from the source clock domain to the target clock domain. The respective values output by the two latches may be compared by a detection circuit, and a value derived from the output value of the first latch and corresponding to the current data may be written to an output latch if the current data differs from the stored previous value. The detection circuit may also provide a defined logical value to the output latch even if the first latch is in a metastable state.

Abstract: In an embodiment, an aging analysis tool may be configured to identify transistors that are expected to experience aging effects according to worst case stress vectors and/or designer identified worst case conditions. The aging analysis tool may modify a representation of the circuit (e.g. a netlist), replacing the identified transistors with aged transistors (e.g. by modifying parameters of the transistors in the netlist). The aging analysis tool may process the modified netlist over a range of conditions at which the circuit is expected to operate, to ensure that the design meets specifications after aging. The process may be repeated until the aged design meets specifications (with circuit modifications made by the designer to improve the design).

Abstract: A mechanism for measuring the variability of the read current of SRAM cells on an integrated circuit includes the integrated circuit having an SRAM array including a plurality of SRAM cells. The integrated circuit may also include a selection circuit configured to select a particular SRAM cell in response to a selection input. An oscillator circuit such as a ring oscillator, for example, on the integrated circuit may be configured to oscillate at a frequency that is dependent upon a read current of a selected SRAM cell during operation in a first mode. A frequency determining circuit that is coupled to the oscillator circuit may be configured to output a value corresponding to the frequency of oscillation of the oscillator circuit.

Abstract: In an embodiment, a clocked storage device such as a pulse flop is provided. The pulse flop includes a latch coupled to receive a scan data input to the pulse flop. The latch receives the scan data input during one of the phases of the clock, and retains the received input during the other phase. The other phase is the phase in which the pulse to the pulse flop occurs. Thus, when scan data is captured in the pulse flop, the latch at the next pulse flop in the chain may be closed and may prevent a race condition in propagating the scan data.

Abstract: A synchronizer circuit for transferring data from a source clock domain to a target clock domain. A first latch in the target clock domain may capture a data value corresponding to current data received from the source clock domain. Under certain conditions, the first latch may enter into a metastable, or undefined logic state. A second latch may remain stable, and store a previous value corresponding to data that has most recently been transferred from the source clock domain to the target clock domain. The respective values output by the two latches may be compared by a detection circuit, and a value derived from the output value of the first latch and corresponding to the current data may be written to an output latch if the current data differs from the stored previous value. The detection circuit may also provide a defined logical value to the output latch even if the first latch is in a metastable state.

Abstract: An apparatus and method for testing level shifter threshold voltages on an integrated circuit includes one or more level shifter modules each including a number of level shifter circuits. Each level shifter circuit may be coupled to a first and a second voltage supply. Each level shifter circuit may also receive an input signal that is referenced to the first voltage supply, and to generate an output signal that is referenced to the second voltage supply. In addition, each level shifter module may include detection logic that may detect an output value of each of the level shifter circuits. The control circuit may be configured to iteratively change the voltage output from one of the voltage supplies, and maintaining a voltage on the other voltage supply while the input signal is provided to the level shifter circuits. The detection logic may capture the output value upon each change in voltage.

Abstract: A synchronizer circuit includes a master stage and a slave stage. The master stage may include a first master latch coupled to receive a data input signal, and a clock signal. The master stage may also include a second master latch coupled to receive the data input signal, and a delayed version of the clock signal. The master stage may further include a pull-up circuit that may drive an output line of the master stage depending upon an output of each of the first master latch and the second master latch. The slave stage may include a slave latch having an input coupled to the output line of the master stage. The slave stage may provide an output data signal that corresponds to the captured input data signal and is synchronized to the receiving clock signal.

Abstract: An apparatus and method for testing sense amplifier threshold voltages on an integrated circuit includes one or more sense amplifier modules each including a number of sense amplifier circuits, a voltage generator unit, and detection logic. The voltage generator unit may select a differential voltage to supply to at least some of the sense amplifier circuits, and each sense amplifier circuit may be configured to generate an output value that is dependent upon the applied differential voltage in response to receiving an enable signal. The detection logic may detect and capture an output value of each of the sense amplifier circuits. In one implementation, the voltage generator unit may iteratively select a different differential voltage in response to a control input. Accordingly, the detection logic may capture the output value of the sense amplifiers after each change in differential voltage.

Abstract: An integrated circuit includes a flip-flop circuit having a master latch unit and a slave latch unit. The master latch unit includes a data latch that may receive a data value on a data input, and a scan latch that may receive a scan data value on a scan data input. The data latch may latch and output the data value on an output line in response to a transition of a first clock signal, while the scan latch may latch and output the scan data value on the output line in response to a transition of a second clock signal. The slave latch unit may latch and output either the data value or the scan data value. The flip-flop circuit also includes a clock select circuit that may selectively provide either the first clock signal or the second clock signal dependent upon a scan enable signal.

Abstract: A mechanism for measuring the variability of the read current of SRAM cells on an integrated circuit includes the integrated circuit having an SRAM array including a plurality of SRAM cells. The integrated circuit may also include a selection circuit configured to select a particular SRAM cell in response to a selection input. An oscillator circuit such as a ring oscillator, for example, on the integrated circuit may be configured to oscillate at a frequency that is dependent upon a read current of a selected SRAM cell during operation in a first mode. A frequency determining circuit that is coupled to the oscillator circuit may be configured to output a value corresponding to the frequency of oscillation of the oscillator circuit.

Abstract: An apparatus and method for testing driver write-ability strength on an integrated circuit includes one or more drive detection units each including a number of drivers. At least some of the drivers may have a different drive strength and each may drive a voltage onto a respective driver output line. Each drive detection unit may include a number of keeper circuits, each coupled to a separate output line and configured to retain a given voltage on the output line to which it is coupled. Each detection unit may also include a number of detection circuits coupled to detect the drive voltage on each of the output lines. In one implementation, the drive voltage appearing at the output line of each driver may be indicative of that the driver was able to overdrive the voltage being retained on the output line to which it is coupled by the respective keeper circuits.

Abstract: An apparatus and method for testing level shifter threshold voltages on an integrated circuit includes one or more level shifter modules each including a number of level shifter circuits. Each level shifter circuit may be coupled to a first and a second voltage supply. Each level shifter circuit may also receive an input signal that is referenced to the first voltage supply, and to generate an output signal that is referenced to the second voltage supply. In addition, each level shifter module may include detection logic that may detect an output value of each of the level shifter circuits. The control circuit may be configured to iteratively change the voltage output from one of the voltage supplies, and maintaining a voltage on the other voltage supply while the input signal is provided to the level shifter circuits. The detection logic may capture the output value upon each change in voltage.

Abstract: A synchronizer circuit includes a master stage and a slave stage. The master stage may include a first master latch coupled to receive a data input signal, and a clock signal. The master stage may also include a second master latch coupled to receive the data input signal, and a delayed version of the clock signal. The master stage may further include a pull-up circuit that may drive an output line of the master stage depending upon an output of each of the first master latch and the second master latch. The slave stage may include a slave latch having an input coupled to the output line of the master stage. The slave stage may provide an output data signal that corresponds to the captured input data signal and is synchronized to the receiving clock signal.

Abstract: A clock gater circuit comprises a plurality of transistors having source-drain connections forming a stack between a first node and a supply node. A given logical state on the first node causes a corresponding logical state on an output clock of the clock gater circuit. In one embodiment, a first transistor of the plurality of transistors has a gate coupled to receive an enable input signal. A second transistor is connected in parallel with the first transistor, and has a gate controlled responsive to a test input signal to ensure that the output clock is generated even if the enable input signal is not in an enabled state. In another embodiment, the plurality of transistors comprises a first transistor having a gate controlled responsive to a clock input of the clock gater circuit and a second transistor having a gate controlled responsive to an output of a delay circuit.

Abstract: A clock gater circuit comprises a plurality of transistors having source-drain connections forming a stack between a first node and a supply node. A given logical state on the first node causes a corresponding logical state on an output clock of the clock gater circuit. In one embodiment, a first transistor of the plurality of transistors has a gate coupled to receive an enable input signal. A second transistor is connected in parallel with the first transistor, and has a gate controlled responsive to a test input signal to ensure that the output clock is generated even if the enable input signal is not in an enabled state. In another embodiment, the plurality of transistors comprises a first transistor having a gate controlled responsive to a clock input of the clock gater circuit and a second transistor having a gate controlled responsive to an output of a delay circuit.

Abstract: A system and method for detecting and preventing race conditions in a circuit is provided. The system includes a first memory element for receiving a data stream. The system further includes a plurality of additional memory elements for directly receiving an output of the data stream from the first memory element. Delay elements are defined between the first memory element and the plurality of additional memory elements other than a second memory element, so that each delay element between the first memory element and the plurality of additional memory elements other than the second memory element are combined to define a sum delay. A plurality of comparators are connected to the plurality of memory elements such that each comparator being configured to compare an input to the first memory element and an output of each of the plurality of additional memory elements.