Abstract: A transistor is added to prior art domino logic circuits to create a modified domino logic circuit with a resistor divider connected between a first internal node and a second internal node. The resistor divider keeps the second internal node at a voltage that is higher than a second supply voltage VSS at the beginning of the evaluation phase of modified domino logic circuit. Consequently, the first internal node of the modified domino logic circuit will not start discharging until a higher voltage is reached by input signals. Thus, the input noise rejection of the modified domino logic circuits of the present invention is improved compared with prior art domino logic circuits.

Abstract: A shut-off circuit included in a dynamic flip-flop isolates output terminals of the dynamic flip-flop from circuitry within the flip-flop that could introduce noise on either output terminal during a portion of the evaluation phase. Since the output terminals are isolated from the input terminals during this portion of the evaluation phase, spurious input signals have no affect on the output signal levels. Similarly, charge within the dynamic flip-flop that is not completely dissipated in the transition from a precharge phase to the evaluation phase has no affect on the output signal levels during this portion of the evaluation phase.

Abstract: A single phase edge-triggered dual-rail dynamic flip-flop circuit for use with dynamic logic gates includes an input stage, precharge stage and buffer. The input stage is coupled to receive a data-input signal and a clock signal. During the precharge phase, the input stage provides an output signal that is the complement of the data input signal. When the data input signal is provided by a dynamic logic gate, the input stage output signal is precharged to a logic high level. During the evaluation phase, the input stage generates an output signal that either remains at a logic high level or else transitions from high-to-low. The precharge stage receives the output signal from the input stage and the clock signal. During the precharge phase, the precharge stage generates a logic high level output signal independently of the signal received from the input stage.

Abstract: A method of implementing a single phase edge-triggered dual-rail dynamic flip-flop circuit for use with dynamic logic gates includes receiving a data-input signal and a clock signal. During the precharge phase, an input stage provides an output signal that is the complement of the data input signal. When the data input signal is provided by a dynamic logic gate, the input stage output signal is precharged to a logic high level. During the evaluation phase, an output signal that either remains at a logic high level or else transitions from high-to-low is generated by the input stage. The output signal and the clock signal are received by the precharge stage from the input stage. During the precharge phase, a logic high level output signal is generated the precharge stage independently of the signal received from the input stage.

Abstract: A method of implementing a scan flipp for use with logic gates includes configuring the flip-flop into a scan mode or data mode. Then the flip-flop enters the precharge phase in which a dynamic input stage is precharged and a static output stage maintains the output signal from the previous evaluation phase. During the evaluation phase in the normal mode, the dynamic input stage generates an output signal that either remains at a logic high level or else transitions from high-to-low, complementing the logic level of the data signal. During the evaluation phase in the scan mode, the dynamic input stage generates an output signal that either remains at a logic high level or else transitions from high-to-low, complementing the logic level of the scan input signal. The static output stage receives the output signal from the dynamic input stage and the clock signal. During the evaluation phase, the static output stage outputs the complement of the output signal received from the dynamic input stage.

Abstract: A non-blocking multiple-phase clocking system for use with domino-type dynamic logic provides clock phases with overlapping evaluation phases to a circuit including a several cascaded dynamic logic gates. The circuit also includes a first flip-flop that is coupled to provide input signal(s) to the first dynamic logic gate of the cascade and a second flip-flop that is coupled to receive output signal(s) from the last dynamic logic gate of the cascade. The clocking system provides a first clock phase to the first dynamic logic gate, a second clock phase to the second dynamic logic gate and so on. A timing analysis is performed of each logic path in the circuit to determine the arrival time of each critical input signals to each dynamic logic gate. The delay between adjacent clock phase is then predetermined so that each dynamic logic gate enters its evaluation phase before the critical input signal(s) to the particular dynamic logic gate arrives.

Abstract: A method for generating non-blocking multiple-phase clocking system for use with domino-type dynamic logic includes receiving a primary clock signal and generating several delayed phases of the received primary clock signal. The number of clock phases equals the number of dynamic logic gates in the circuit. The method provides a first clock phase to the first dynamic logic gate of the circuit, a second clock phase to the second dynamic logic gate and so on. A timing analysis is performed of each logic path in the circuit to determine the arrival time of each critical input signals to each dynamic logic gate. The delay between adjacent clock phase is then predetermined so that each dynamic logic gate enters its evaluation phase before the critical input signal(s) to the particular dynamic logic gate arrives. This adjustment of the clock phases maximizes the logic evaluation speed of the dynamic logic circuit.

Abstract: A flip-flop circuit for use with logic gates includes a dynamic input stage and a static output stage. The flip-flop receives a single phase which defines a precharge phase and an evaluation phase. The dynamic input stage has a NMOS logic block coupled to receive one or more data signals. The dynamic input stage output signal is precharged to a logic high level during the precharge phase. During the evaluation phase, the NMOS logic block of the dynamic input stage causes the dynamic input stage to generate an output signal that either remains at a logic high level or else transitions from high-to-low by performing a logic operation of the data signals. The static output stage receives the output signal from the dynamic input stage and the clock signal. During the precharge phase, the static output stage maintains the flip-flop output signal logic at the logic level of the previous evaluation phase independently of the signal received from the dynamic input stage.

Abstract: A single phase edge-triggered dual-rail dynamic flip-flop circuit for use with dynamic logic gates includes an input stage, precharge stage and buffer. The input stage is coupled to receive a data-input signal and a clock signal. During the precharge phase, the input stage provides an output signal that is the complement of the data input signal. When the data input signal is provided by a dynamic logic gate, the input stage output signal is precharged to a logic high level. During the evaluation phase, the input stage generates an output signal that either remains at a logic high level or else transitions from high-to-low. The precharge stage receives the output signal from the input stage and the clock signal. During the precharge phase, the precharge stage generates a logic high level output signal independently of the signal received from the input stage.

Abstract: A single phase edge-triggered staticized dynamic flip-flop circuit for use with dynamic logic gates includes a dynamic input stage and a static output stage. The dynamic input stage is coupled to receive a data signal and a clock signal. During the precharge phase, the dynamic input stage provides an output signal that is the complement of the data signal. The dynamic input stage output signal is precharged to a logic high level during the precharge phase. During the evaluation phase, the dynamic input stage generates an output signal that either remains at a logic high level or else transitions from high-to-low, complementing the logic level of the data signal. The static output stage receives the output signal from the dynamic input stage and the clock signal. During the precharge phase, the static output stage maintains the flip-flop output signal logic at the logic level of the previous evaluation phase independently of the signal received from the dynamic input stage.

Abstract: A flip-flop circuit with scan circuitry for use with static logic gates includes a dynamic input stage and a static output stage. The dynamic input stage is coupled to receive a data signal, a scan input signal, a scan enable signal, a data enable signal and a single-phase clock signal. During the precharge phase, the dynamic input stage provides an output signal that is the complement of the data or the scan signal. The dynamic input stage output signal is precharged to a logic high level during the precharge phase. During the precharge phase, the static output stage maintains the flip-flop output signal logic at the logic level of the previous evaluation phase independently of the signal received from the dynamic input stage. During the evaluation phase in the normal mode, the dynamic input stage generates an output signal that either remains at a logic high level or else transitions from high-to-low, complementing the logic level of the data signal.

Abstract: A dynamic logic signal repeater includes a complementary dynamic logic circuit with an input node to receive an input signal and an output node storing a precharge signal. The complementary dynamic logic circuit configuration, transistor sizing, and the use of a precharge driver results in a signal transition trip point for the precharge signal on the output node that is substantially equivalent to the signal transition trip point of a static logic circuit. Thus, the dynamic logic signal repeater has improved noise immunity. An evaluation locking transistor is connected to the complementary dynamic logic circuit and the output node. The evaluation locking transistor prevents the charging of the output node during a dynamic logic evaluation period.

Abstract: A non-blocking multiple-phase clocking system for use with dynamic logic provides clock phases with overlapping evaluation phases to a circuit including a several cascaded dynamic logic gates. The circuit also includes a first flip-flop that is coupled to provide input signal(s) to the first dynamic logic gate of the cascade and a second flip-flop that is coupled to receive output signal(s) from the last dynamic logic gate of the cascade. Through the use of the overlapping evaluation phases and proper assignment of the clock signals to the dynamic logic gates, the output signal(s) generated by the dynamic logic gates receiving a particular clock phase are used as input signals to the dynamic logic gates receiving the next clock phase. Because of the overlapping of the clock phases, no latch is used. The clock phases are assigned to a particular dynamic logic gate so that the this dynamic logic gate enters the evaluation phase before the input signal(s) to the particular dynamic logic gate arrives (i.e.

Abstract: A dynamic flip-flop includes a first input latch coupled to receive a data input signal and a second input latch coupled to receive the complement of the data put signal. The first and second input latches have first and second shutoff circuits, respectively. During a precharge phase, the first and second input latches each provide an output signal of a first logic level. During an evaluation phase, the first and second input latches sample the data input signal and complemented data input signal, respectively. In response to the samples of true and the complement of the data input signal, one input latch's output signal will transition to a second logic level, while the other input latch's output signal will remain at the first logic level. A first output latch and a second output latch are coupled to receive the output signals of the first and second input latches, respectively. The first and second output latches are inverting.