Abstract: A system and method for unifying access to a physical memory by operations using virtual addresses of the same virtual address space are provided. The operations may be generated by at least one central processing unit (CPU operations) and/or by at least one IO device (IO operations). The system may include a bus arranged to transfer data and virtual addresses of the same virtual address space from the central processing unit (CPU) and the IO device to a unified memory management unit (UMMU), a unified memory management unit (UMMU) arranged to translate the virtual addresses to physical addresses, and to protect the physical memory from illegal access attempts of the CPU operations and the IO operations. The system may further include a memory controller arranged to manage access to the physical memory. The access is done by using physical addresses.

Abstract: A method for wiring allocation and switch configuration in a multiprocessor computer, the method including employing depth-first tree traversal to determine a plurality of paths among a plurality of processing elements allocated to a job along a plurality of switches and wires in a plurality of D-lines, and selecting one of the paths in accordance with at least one selection criterion.

Abstract: Exemplary embodiments of the present invention comprise a method for the utilization of entry-replacement index hint information within a software-managed TLB. The method comprises receiving an address translation request at a TLB and retrieving the address translation information from a page table in the event of a miss lookup event at the TLB. The method further comprises retrieving index replacement hint information from a hardware component, wherein the hardware component is configured to execute a predetermined replacement algorithm and writing the address translation information to a TLB index referenced within the index replacement hint information.

Abstract: A method for job selection and resource allocation of massively parallel processors, the method includes: providing to a constraint satisfaction problem solver multiple domains, variables, and constraints representative of a massively parallel processor, of queued job requests and of jobs being processed by the massively parallel processor, and generating, by the constraint satisfaction problem solver a result representative of multiple jobs to be executed, at least partially in parallel, by multiple resources of the massively parallel processor.

Abstract: A method for wiring allocation and switch configuration in a multiprocessor computer, the method including employing depth-first tree traversal to determine a plurality of paths among a plurality of processing elements allocated to a job along a plurality of switches and wires in a plurality of D-lines, and selecting one of the paths in accordance with at least one selection criterion.

Abstract: The present invention provides a fault tolerant system and method for parallel job execution. In the proposed solution the job state and the state transition control are decoupled. The job execution infrastructure maintains the state information for all the executing jobs, and the job control units, one per-job, control the state transitions of their jobs. Due to the stateless nature of the control units, the system and method allow jobs to continue uninterrupted execution even when the corresponding control units fail.

Abstract: A system and method for unifying access to a physical memory by operations using virtual addresses of the same virtual address space are provided. The operations may be generated by at least one central processing unit (CPU operations) and/or by at least one IO device (IO operations). The system may include a bus arranged to transfer data and virtual addresses of the same virtual address space from the central processing unit (CPU) and the IO device to a unified memory management unit (UMMU), a unified memory management unit (UMMU) arranged to translate the virtual addresses to physical addresses, and to protect the physical memory from illegal access attempts of the CPU operations and the IO operations. The system may further include a memory controller arranged to manage access to the physical memory. The access is done by using physical addresses.

Abstract: A method for wiring allocation and switch configuration in a multiprocessor computer, the method including employing depth-first tree traversal to determine a plurality of paths among a plurality of processing elements allocated to a job along a plurality of switches and wires in a plurality of D-lines, and selecting one of the paths in accordance with at least one selection criterion.