Abstract: Various method and apparatus embodiments for training a delay for enabling a data strobe signal in a memory subsystem are disclosed. In one embodiment, a system includes a memory controller configured to receive a data strobe signal. The memory controller includes a training circuit. The training circuit includes a first storage circuit coupled to receive the data strobe signal on a data input and an enable signal on a clock input, and a training unit configured to, based on an output signal received from the first flip-flop, adjust a phase of the enable signal until an assertion of the enable signal coincides with a preamble indication in the data strobe signal.

Abstract: A decision feedback equalization (DFE) receiver and method are provided. The DFE receiver is configured to sample data bits from a data bus. The DFE receiver includes a data sampler configured to sample a current data bit from the data bus using one of a first, second and third voltage reference. The DFE receiver also includes multiplexing logic configured to select one of the first, second and third voltage references based on a prior data bus level. The wherein the first voltage reference is selected if the prior data bus level was a logic zero. The second voltage reference is selected if the prior data bus level was a logic one. The third voltage reference is selected if the prior data bus level was tri-state.

Abstract: A method is provided for sampling a data strobe signal of a memory cycle and determining a receiver enable phase based upon the data strobe signal. The method also includes performing a memory write cycle and a subsequent read cycle and training a read data strobe cycle at a one-quarter memory clock periodic offset. The method also includes determining a correct receiver enable delay in response to a successful read data strobe training cycle. Computer readable storage media are also provided. An apparatus is provided that includes a communication interface portion that is coupled to a memory portion and to a processing device. The apparatus also includes a first circuit portion, coupled to the communication interface portion. The first circuit portion monitors memory cycles on the communication interface portion, determines a receiver enable cycle phase and train a receiver enable cycle without using receiver enable seed.

Abstract: A system and method of data communications between a first device and a second device is disclosed. The method includes generating a first clock signal at the first device and generating a second clock signal having a phase offset from the first clock signal. The clock signals are transmitted from the first device to the second device. The method further includes regulating transmission of a read strobe signal sent from the second device to the first device utilizing the first clock signal. The method also includes regulating transmission of a data transfer signal sent from the second device to the first device utilizing the second clock signal.

Abstract: A decision feedback equalization (DFE) receiver and method are provided. The DFE receiver is configured to sample data bits from a data bus. The DFE receiver includes a data sampler configured to sample a current data bit from the data bus using one of a first, second and third voltage reference. The DFE receiver also includes multiplexing logic configured to select one of the first, second and third voltage references based on a prior data bus level. The wherein the first voltage reference is selected if the prior data bus level was a logic zero. The second voltage reference is selected if the prior data bus level was a logic one. The third voltage reference is selected if the prior data bus level was tri-state.

Abstract: An apparatus for providing a signal for transmission via a signal line includes a controller circuit having an output for a signal indicating whether the signal line is or will be in an inactive state and a switching circuit coupled to the controller circuit and having an output coupled to the signal line. The output is switched between different signal levels, if the signal indicates that the signal line is in an inactive state.

Abstract: An arrangement for generating a transmission clock signal and a reception clock signal is proposed in which only a single voltage-controlled oscillator is used, the reception clock signal being generated by phase-adjusting means whereas the transmission clock signal is generated directly by the voltage-controlled oscillator. Cross-talk between a plurality of voltage-controlled oscillators can be prevented in this way. Also, various measures are proposed for optimizing a circuit of this kind.

Abstract: A data sampler including a first stage and a second stage. The first stage is configured to receive differential signals and provide a first edge rate in a first output signal and a second edge rate in a second output signal based on the differential signals. The second stage is configured to amplify the difference between the first output signal and the second output signal to provide regenerated output signals. The second stage provides a third edge rate in a first internal signal and a fourth edge rate in a second internal signal based on the first edge rate and the second edge rate.

Abstract: An apparatus being connectable as a latch stage into a asynchronous latch chain comprises a reception interface, wherein upon receipt of the first signal at the reception interface, the apparatus switches to one of the first power saving mode and a second power saving mode, depending on the second signal at the reception interface and wherein the apparatus offers a first power consumption and a first wake-up time in the first power saving mode, and a second power consumption and a second wake-up time in the second power saving mode.

Abstract: A clock and data recovery circuit includes a phase detector configured to compare a phase of a data signal to a phase of a sampling clock to provide a phase error signal, a gain stage configured to apply a gain to the phase error signal to provide an amplified phase error signal, and a filter configured to filter the amplified phase error signal to provide a phase correction signal. The circuit includes a gain controller configured to adjust the gain of the gain stage in response to the phase correction signal, and a clock generator configured to provide the sampling clock based on the phase correction signal.

Abstract: A clock signal extraction device for extracting a clock signal from a periodic data signal includes a phase detector for detecting a first phase difference between rising edges of said data signal and a rising edges clock signal and for detecting a second phase difference between falling edges of said data signal and a falling edges clock signal. The device also includes a clock generator for generating said rising edges clock signal so that said first phase difference is minimized, for generating said falling edges clock signal so that said second phase difference is minimized, and for generating said clock signal in dependence on said first phase difference and said second phase difference. A method for extracting a clock signal from a periodic data signal is related to the device.

Abstract: Method and arrangement for generating an output clock signal with an adjustable phase relation from a plurality of input clock signals. A method and an arrangement are provided for generating an output clock signal (o), in which a plurality of input clock signals (s, c) that have a predetermined phase relationship to one another, are weighted with respective weighting factors (A, 1-A), and in which the weighted input clock signals (s?, c?) are added in order to generate a summated clock signal (i). The summated clock signal (i) is integrated in an integrator (8) and optionally amplified in order to generate the output clock signal (o). An output clock signal (o) with an adjustable phase relation can be generated with such a method and such an arrangement, in which the requirements placed on the input clock signals are less stringent.

Abstract: An apparatus interfaces a first circuit using a first supply voltage and a second circuit using a second supply voltage different from the first supply voltage. The apparatus includes a driver circuit having a driver network comprising driver supply voltage terminals connected to controllable switches. The controllable switches include resistive elements or are separated from resistive elements. A receiver circuit has a receiving network comprising a resistive element and receiver supply voltage terminals and a connection line connecting the driver circuit and the receiving circuit. The controllable switches have two switch configurations, a first switch configuration resulting in a high voltage on the connection line and a second switch configuration resulting in a low voltage on the connection line.

Abstract: An apparatus for providing a signal for transmission via a signal line includes a controller circuit having an output for a signal indicating whether the signal line is or will be in an inactive state and a switching circuit coupled to the controller circuit and having an output coupled to the signal line. The output is switched between different signal levels, if the signal indicates that the signal line is in an inactive state.

Abstract: An apparatus interfaces a first circuit using a first supply voltage and a second circuit using a second supply voltage different from the first supply voltage. The apparatus includes a driver circuit having a driver network comprising driver supply voltage terminals connected to controllable switches. The controllable switches include resistive elements or are separated from resistive elements. A receiver circuit has a receiving network comprising a resistive element and receiver supply voltage terminals and a connection line connecting the driver circuit and the receiving circuit. The controllable switches have two switch configurations, a first switch configuration resulting in a high voltage on the connection line and a second switch configuration resulting in a low voltage on the connection line.

Abstract: A memory buffer comprises a first asynchronous latch chain interface connectable to at least one of a memory controller and a memory buffer, a second data interface connected to a memory device, and a circuit comprising a buffer and a processor, the circuit being coupled to the first and the second interfaces, so that data can be passed between the first interface and the buffer and between the second interface and the buffer and so that the processor is capable of processing at least one of the data from the first interface to the second interface and the data from the second interface according to a data processing functionality, wherein the data processing functionality of the processor is changeable by a programming signal received via an interface of a memory buffer.

Abstract: An apparatus for transmitting signals over a signal line includes a transmitter with an output connectable to the signal line, for a synchronization signal in a power saving mode and a wanted signal in a normal mode of operation, wherein the synchronization signal has a reduced amplitude as compared to an amplitude of the wanted signal and has a periodic data pattern so that the synchronization signal permits maintaining an alignment of the synchronization signal and a reference signal in the receiver.

Abstract: An apparatus being connectable as a latch stage into a asynchronous latch chain comprises a reception interface, wherein upon receipt of the first signal at the reception interface, the apparatus switches to one of the first power saving mode and a second power saving mode, depending on the second signal at the reception interface and wherein the apparatus offers a first power consumption and a first wake-up time in the first power saving mode, and a second power consumption and a second wake-up time in the second power saving mode.

Abstract: A data sampler including a first stage and a second stage. The first stage is configured to receive differential signals and provide a first edge rate in a first output signal and a second edge rate in a second output signal based on the differential signals. The second stage is configured to amplify the difference between the first output signal and the second output signal to provide regenerated output signals. The second stage provides a third edge rate in a first internal signal and a fourth edge rate in a second internal signal based on the first edge rate and the second edge rate.

Abstract: The present invention relates to a method and apparatus for generating an output signal in dependence on a phase difference between two periodic signals. The present invention is particularly useful in phase locked loops and delay locked loops, in which a controllable oscillator or a controllable delay device is controlled on the basis of the phase difference determined by means of phase detection, in such a way that a control signal can be obtained, the phase lag or frequency of which has a firm relationship to the reference signal.