Abstract: The present invention refers to a memory system with a controller and a memory device with a communication channel with a data path and a timing path coupling the controller with the memory device. The communication channel has different propagation times for the data path and the timing path exchanging a information signal and a timing signal between the controller and the memory device. The timing signals are used for determining the value of the information signal, and a retiming circuit that is connected with the communication channel compensates, depending on a compensation signal on an input, the delay between the data path and the timing path for exchanging a information signal and a timing signal between the controller and the memory device.

Abstract: A clock and data recovery circuit including a first circuit and a second circuit. The first circuit is configured to receive a clock signal and a phase control signal and to lock onto the clock signal and provide a cleaned clock signal. The second circuit is configured to receive a data signal and the cleaned clock signal and to sample the data signal via the cleaned clock signal and provide the phase control signal. The first circuit adjusts the phase of the cleaned clock signal based on the phase control signal.

Abstract: A clock and data recovery circuit includes a phase detector configured to compare a phase of a data signal to a phase of a sampling clock to provide a phase error signal, a gain stage configured to apply a gain to the phase error signal to provide an amplified phase error signal, and a filter configured to filter the amplified phase error signal to provide a phase correction signal. The circuit includes a gain controller configured to adjust the gain of the gain stage in response to the phase correction signal, and a clock generator configured to provide the sampling clock based on the phase correction signal.

Abstract: A method of receiving data includes sampling the data at data sampling points to obtain data samples corresponding to information contained in the data, and sampling the data at intermediate sampling points between the data sampling points to obtain intermediate samples. The data is corrected at at least one intermediate sampling point of the intermediate sampling points depending on at least one of a previous data sample sampled at a data sampling point preceding the at least one intermediate sampling point and a previous intermediate sample sampled at a data sampling point preceding the at least one intermediate sampling point.

Abstract: Method and arrangement for generating an output clock signal with an adjustable phase relation from a plurality of input clock signals. A method and an arrangement are provided for generating an output clock signal (o), in which a plurality of input clock signals (s, c) that have a predetermined phase relationship to one another, are weighted with respective weighting factors (A, 1-A), and in which the weighted input clock signals (s?, c?) are added in order to generate a summated clock signal (i). The summated clock signal (i) is integrated in an integrator (8) and optionally amplified in order to generate the output clock signal (o). An output clock signal (o) with an adjustable phase relation can be generated with such a method and such an arrangement, in which the requirements placed on the input clock signals are less stringent.

Abstract: The invention provides a clock signal extraction device for extracting a clock signal from a periodic data signal, comprising a phase detector (104, 106) for detecting a first phase difference between rising edges of said data signal and a rising edges clock signal and for detecting a second phase difference between falling edges of said data signal and a falling edges clock signal; and a clock generator (110, 112) for generating said rising edges clock signal so that said first phase difference is minimized, for generating said falling edges clock signal so that said second phase difference is minimized, and for generating said clock signal in dependence on said first phase difference and said second phase difference. The invention further provides a method for extracting a clock signal from a periodic data signal.

Abstract: To generate an output signal (11) the frequency of which is twice the frequency of an input signal (1, 2), a delayed signal (3, 4) which is delayed relative to the input signal (1, 2) by a quarter of the latter's cycle period is generated and the output signal (11) is then generated as the difference between the rectified input signal (1, 2) and the rectified delayed signal (3, 4). The input signal (1, 2) and the delayed signal (3, 4) are advantageously rectified by using differential signals each comprising a positive component signal (1, 3) and a negative component signal (2, 4). A respective one of two transistors connected in parallel is driven by a positive component signal (1, 3) and a negative component signal (2, 4) in such a way that a positive half-wave causes the relevant transistor (5-8) to conduct and the relevant transistor (5-8) blocks in a negative half-wave.

Abstract: For the detection of a phase difference between a reference signal (6) and a control signal, the reference signal (6) is sampled at fixed sampling time points (S1-S7), whereby the gaps between the sampling time points (S1-S7) are variable. An output signal (PD0-PD6), which can only assume a certain number of possible states, is generated in dependence on the samplings (A0-A6) obtained at the sampling time points (S1-S7). In the case of binary sampling of the reference signal (6), the samplings (A0-A6) are present as a binary word, which can be illustrated by means of suitable logic on output signals (PD0-PD6), which again represent the various states of the output signal. Preferably, each state is depicted by the active state of an output line (PD0-PD6).

Abstract: To generate an output signal (11) the frequency of which is twice the frequency of an input signal (1, 2), a delayed signal (3, 4) which is delayed relative to the input signal (1, 2) by a quarter of the latter's cycle period is generated and the output signal (11) is then generated as the difference between the rectified input signal (1, 2) and the rectified delayed signal (3, 4). The input signal (1, 2) and the delayed signal (3, 4) are advantageously rectified by using differential signals each comprising a positive component signal (1, 3) and a negative component signal (2, 4). A respective one of two transistors connected in parallel is driven by a positive component signal (1, 3) and a negative component signal (2, 4) in such a way that a positive half-wave causes the relevant transistor (5-8) to conduct and the relevant transistor (5-8) blocks in a negative half-wave.