Patents by Inventor Edward C McGlaughlin
Edward C McGlaughlin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11868267Abstract: A system includes a first memory component having a particular access size associated with performance of memory operations, a second memory component to store a logical to physical data structure whose entries map management segments to respective physical locations in the memory component, wherein each management segment corresponds to an aggregated plurality of logical access units having the particular access size, and a processing device, operably coupled to the memory component. The processing device can perform memory management operations on a per management segment basis by: for each respective management segment, tracking access requests to constituent access units corresponding to the respective management segment, and determining whether to perform a particular memory management operation on the respective management segment based on the tracking.Type: GrantFiled: March 30, 2022Date of Patent: January 9, 2024Assignee: Micron Technology, Inc.Inventors: Edward C. McGlaughlin, Gary J. Lucas, Joseph M. Jeddeloh
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Patent number: 11657872Abstract: An example method includes determining a time between writes in place to a particular memory cell, incrementing a disturb count corresponding to a neighboring memory cell by a particular count increment that is based on the time between the writes to the particular memory cell, and determining whether to check a write disturb status of the neighboring memory cell based on the incremented disturb count.Type: GrantFiled: August 30, 2021Date of Patent: May 23, 2023Assignee: Micron Technology, Inc.Inventors: Edward C. McGlaughlin, Samuel E. Bradshaw
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Patent number: 11556465Abstract: An example method includes maintaining a first data structure comprising logical address to physical address mappings for managed units corresponding to a memory, and maintaining a second data structure whose entries correspond to respective physical managed unit addresses. Each entry of the second data structure comprises an activity counter field corresponding to the respective physical managed unit address and a number of additional fields indicating whether the respective physical managed unit address is in one or more of a number of additional data structures. The one or more additional data structures are accessed in association with performing at least one of a wear leveling operation on the respective physical managed unit address, and a neighbor disturb mitigation operation on physical managed unit addresses corresponding to neighbors of the respective physical managed unit address.Type: GrantFiled: February 12, 2021Date of Patent: January 17, 2023Assignee: Micron Technology, Inc.Inventors: Edward C. McGlaughlin, Joseph M. Jeddeloh
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Patent number: 11544144Abstract: An apparatus includes an error correction component coupled to read recovery control circuitry. The error correction component can be configured to perform one or more initial error correction operations on codewords contained within a managed unit received thereto. The read recovery control circuitry can be configured to receive the error corrected codewords from the error correction component and determine whether codewords among the error corrected codewords contain an uncorrectable error. The read recovery control circuitry can be further configured to determine that a redundant array of independent disks (RAID) codeword included in the plurality of error corrected codewords contains the uncorrectable error, request that codewords among the error corrected codewords that contain the uncorrectable error are rewritten in response to the determination, and cause the plurality of error corrected codewords to be transferred to a host coupleable to the read recovery control circuitry.Type: GrantFiled: May 19, 2021Date of Patent: January 3, 2023Assignee: Micron Technology, Inc.Inventors: Richard D. Wiita, Edward C. McGlaughlin, Gary J. Lucas
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Publication number: 20220222181Abstract: A system includes a first memory component having a particular access size associated with performance of memory operations, a second memory component to store a logical to physical data structure whose entries map management segments to respective physical locations in the memory component, wherein each management segment corresponds to an aggregated plurality of logical access units having the particular access size, and a processing device, operably coupled to the memory component. The processing device can perform memory management operations on a per management segment basis by: for each respective management segment, tracking access requests to constituent access units corresponding to the respective management segment, and determining whether to perform a particular memory management operation on the respective management segment based on the tracking.Type: ApplicationFiled: March 30, 2022Publication date: July 14, 2022Inventors: Edward C. McGlaughlin, Gary J. Lucas, Joseph M. Jeddeloh
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Patent number: 11301391Abstract: A system includes a first memory component having a particular access size associated with performance of memory operations, a second memory component to store a logical to physical data structure whose entries map management segments to respective physical locations in the memory component, wherein each management segment corresponds to an aggregated plurality of logical access units having the particular access size, and a processing device, operably coupled to the memory component. The processing device can perform memory management operations on a per management segment basis by: for each respective management segment, tracking access requests to constituent access units corresponding to the respective management segment, and determining whether to perform a particular memory management operation on the respective management segment based on the tracking.Type: GrantFiled: August 31, 2020Date of Patent: April 12, 2022Assignee: Micron Technology, Inc.Inventors: Edward C. McGlaughlin, Gary J. Lucas, Joseph M. Jeddeloh
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Publication number: 20210391007Abstract: An example method includes determining a time between writes in place to a particular memory cell, incrementing a disturb count corresponding to a neighboring memory cell by a particular count increment that is based on the time between the writes to the particular memory cell, and determining whether to check a write disturb status of the neighboring memory cell based on the incremented disturb count.Type: ApplicationFiled: August 30, 2021Publication date: December 16, 2021Inventors: Edward C. McGlaughlin, Samuel E. Bradshaw
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Publication number: 20210373887Abstract: An apparatus includes a memory component, a delay component, and a command component coupled to the delay component. The command component can be configured to enter a received command associated with accessing a physical address in the memory component into an execution queue and mark the command as active. The command component can be configured to send the active command to the memory component to be executed. The command component can be configured to clear the active command from the execution queue in response to receiving a message from the memory component, via the delay component, indicating the active command has been executed. The delay component can be configured to delay the message from the memory component a particular period of time before sending the message to the command component.Type: ApplicationFiled: August 16, 2021Publication date: December 2, 2021Inventors: Bruce Dunlop, Gary J. Lucas, Edward C. McGlaughlin
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Patent number: 11133061Abstract: An example method includes determining a time between writes in place to a particular memory cell, incrementing a disturb count corresponding to a neighboring memory cell by a particular count increment that is based on the time between the writes to the particular memory cell, and determining whether to check a write disturb status of the neighboring memory cell based on the incremented disturb count.Type: GrantFiled: March 9, 2020Date of Patent: September 28, 2021Assignee: Micron Technology, Inc.Inventors: Edward C. McGlaughlin, Samuel E. Bradshaw
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Publication number: 20210271548Abstract: An apparatus includes an error correction component coupled to read recovery control circuitry. The error correction component can be configured to perform one or more initial error correction operations on codewords contained within a managed unit received thereto. The read recovery control circuitry can be configured to receive the error corrected codewords from the error correction component and determine whether codewords among the error corrected codewords contain an uncorrectable error. The read recovery control circuitry can be further configured to determine that a redundant array of independent disks (RAID) codeword included in the plurality of error corrected codewords contains the uncorrectable error, request that codewords among the error corrected codewords that contain the uncorrectable error are rewritten in response to the determination, and cause the plurality of error corrected codewords to be transferred to a host coupleable to the read recovery control circuitry.Type: ApplicationFiled: May 19, 2021Publication date: September 2, 2021Inventors: Richard D. Wiita, Edward C. McGlaughlin, Gary J. Lucas
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Patent number: 11093244Abstract: An apparatus includes a memory component, a delay component, and a command component coupled to the delay component. The command component can be configured to enter a received command associated with accessing a physical address in the memory component into an execution queue and mark the command as active. The command component can be configured to send the active command to the memory component to be executed. The command component can be configured to clear the active command from the execution queue in response to receiving a message from the memory component, via the delay component, indicating the active command has been executed. The delay component can be configured to delay the message from the memory component a particular period of time before sending the message to the command component.Type: GrantFiled: August 28, 2019Date of Patent: August 17, 2021Assignee: Micron Technology, Inc.Inventors: Bruce Dunlop, Gary J. Lucas, Edward C. McGlaughlin
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Publication number: 20210165738Abstract: An example method includes maintaining a first data structure comprising logical address to physical address mappings for managed units corresponding to a memory, and maintaining a second data structure whose entries correspond to respective physical managed unit addresses. Each entry of the second data structure comprises an activity counter field corresponding to the respective physical managed unit address and a number of additional fields indicating whether the respective physical managed unit address is in one or more of a number of additional data structures. The one or more additional data structures are accessed in association with performing at least one of a wear leveling operation on the respective physical managed unit address, and a neighbor disturb mitigation operation on physical managed unit addresses corresponding to neighbors of the respective physical managed unit address.Type: ApplicationFiled: February 12, 2021Publication date: June 3, 2021Inventors: Edward C. McGlaughlin, Joseph M. Jeddeloh
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Patent number: 11023317Abstract: An apparatus includes an error correction component coupled to read recovery control circuitry. The error correction component can be configured to perform one or more initial error correction operations on codewords contained within a managed unit received thereto. The read recovery control circuitry can be configured to receive the error corrected codewords from the error correction component and determine whether codewords among the error corrected codewords contain an uncorrectable error. The read recovery control circuitry can be further configured to determine that a redundant array of independent disks (RAID) codeword included in the plurality of error corrected codewords contains the uncorrectable error, request that codewords among the error corrected codewords that contain the uncorrectable error are rewritten in response to the determination, and cause the plurality of error corrected codewords to be transferred to a host coupleable to the read recovery control circuitry.Type: GrantFiled: July 12, 2019Date of Patent: June 1, 2021Assignee: Micron Technology, Inc.Inventors: Richard D. Wiita, Edward C. McGlaughlin, Gary J. Lucas
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Publication number: 20210064369Abstract: An apparatus includes a memory component, a delay component, and a command component coupled to the delay component. The command component can be configured to enter a received command associated with accessing a physical address in the memory component into an execution queue and mark the command as active. The command component can be configured to send the active command to the memory component to be executed. The command component can be configured to clear the active command from the execution queue in response to receiving a message from the memory component, via the delay component, indicating the active command has been executed. The delay component can be configured to delay the message from the memory component a particular period of time before sending the message to the command component.Type: ApplicationFiled: August 28, 2019Publication date: March 4, 2021Inventors: Bruce Dunlop, Gary J. Lucas, Edward C. McGlaughlin
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Publication number: 20210064368Abstract: An apparatus includes a memory device and command component coupled to the memory component. The command component can be configured to receive commands associated with accessing a physical address in the memory device. The command component can be further configured to track which of the received commands are active, wherein an active command is a command that is ready to be executed and track which of the received commands are pending, wherein a pending command is a command that is waiting for a previously received command associated with a same physical address to be executed. In response to the previously received command being associated with the same physical address being executed, the command component is configured to convert the pending command to an active command.Type: ApplicationFiled: August 28, 2019Publication date: March 4, 2021Inventors: Bruce Dunlop, Gary J. Lucas, Edward C. McGlaughlin
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Patent number: 10922221Abstract: An example method includes maintaining a first data structure comprising logical address to physical address mappings for managed units corresponding to a memory, and maintaining a second data structure whose entries correspond to respective physical managed unit addresses. Each entry of the second data structure comprises an activity counter field corresponding to the respective physical managed unit address and a number of additional fields indicating whether the respective physical managed unit address is in one or more of a number of additional data structures. The one or more additional data structures are accessed in association with performing at least one of a wear leveling operation on the respective physical managed unit address, and a neighbor disturb mitigation operation on physical managed unit addresses corresponding to neighbors of the respective physical managed unit address.Type: GrantFiled: March 28, 2018Date of Patent: February 16, 2021Assignee: Micron Technology, Inc.Inventors: Edward C. McGlaughlin, Joseph M. Jeddeloh
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Publication number: 20210011804Abstract: An apparatus includes an error correction component coupled to read recovery control circuitry. The error correction component can be configured to perform one or more initial error correction operations on codewords contained within a managed unit received thereto. The read recovery control circuitry can be configured to receive the error corrected codewords from the error correction component and determine whether codewords among the error corrected codewords contain an uncorrectable error. The read recovery control circuitry can be further configured to determine that a redundant array of independent disks (RAID) codeword included in the plurality of error corrected codewords contains the uncorrectable error, request that codewords among the error corrected codewords that contain the uncorrectable error are rewritten in response to the determination, and cause the plurality of error corrected codewords to be transferred to a host coupleable to the read recovery control circuitry.Type: ApplicationFiled: July 12, 2019Publication date: January 14, 2021Inventors: Richard D. Wiita, Edward C. McGlaughlin, Gary J. Lucas
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Publication number: 20200394140Abstract: A system includes a first memory component having a particular access size associated with performance of memory operations, a second memory component to store a logical to physical data structure whose entries map management segments to respective physical locations in the memory component, wherein each management segment corresponds to an aggregated plurality of logical access units having the particular access size, and a processing device, operably coupled to the memory component. The processing device can perform memory management operations on a per management segment basis by: for each respective management segment, tracking access requests to constituent access units corresponding to the respective management segment, and determining whether to perform a particular memory management operation on the respective management segment based on the tracking.Type: ApplicationFiled: August 31, 2020Publication date: December 17, 2020Inventors: Edward C. McGlaughlin, Gary J. Lucas, Joseph M. Jeddeloh
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Patent number: 10817430Abstract: A system includes a first memory component having a particular access size associated with performance of memory operations, a second memory component to store a logical to physical data structure whose entries map management segments to respective physical locations in the memory component, wherein each management segment corresponds to an aggregated plurality of logical access units having the particular access size, and a processing device, operably coupled to the memory component. The processing device can perform memory management operations on a per management segment basis by: for each respective management segment, tracking access requests to constituent access units corresponding to the respective management segment, and determining whether to perform a particular memory management operation on the respective management segment based on the tracking.Type: GrantFiled: October 2, 2018Date of Patent: October 27, 2020Assignee: Micron Technology, Inc.Inventors: Edward C. McGlaughlin, Gary J. Lucas, Joseph M. Jeddeloh
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Publication number: 20200211645Abstract: An example method includes determining a time between writes in place to a particular memory cell, incrementing a disturb count corresponding to a neighboring memory cell by a particular count increment that is based on the time between the writes to the particular memory cell, and determining whether to check a write disturb status of the neighboring memory cell based on the incremented disturb count.Type: ApplicationFiled: March 9, 2020Publication date: July 2, 2020Inventors: Edward C. McGlaughlin, Samuel E. Bradshaw