Abstract: A CMOS active pixel sensor (APS) cell structure having dual workfunction transfer gate device and method of fabrication. The transfer gate device comprises a dielectric layer formed on a substrate and a dual workfunction gate conductor layer formed on the dielectric layer comprising a first conductivity type doped region and an abutting second conductivity type doped region. The transfer gate device defines a channel region where charge accumulated by a photosensing device is transferred to a diffusion region. A silicide structure is formed atop the dual workfunction gate conductor layer for electrically coupling the first and second conductivity type doped regions. In one embodiment, the silicide contact is smaller in area dimension than an area dimension of said dual workfunction gate conductor layer. Presence of the silicide strap prevents the diodic behavior from allowing one or the other side of the gate to float to an indeterminate voltage.

Abstract: A video conferencing method is provided in a system for managing voice and data communications to a plurality of users. Computer data is communicated between the system and one of a plurality of computers coupled to the system over one or more packet buses. Voice data is communicated between the system and one of a plurality of telephone devices coupled to the system. The voice data is coupled to a TDM bus in the system, and the voice data and/or the computer data are coupled from the TDM bus to a digital transmission link. Video and audio data are coupled between the system and a video conferencing unit and coupled to the TDM bus. The video and audio data are coupled from the TDM bus to a digital transmission link of the telecommunications network. A video conference participant participates in a video conference with the video conferencing unit over the digital transmission link, while concurrently a user participates in a telephone call with one of the telephone devices over the digital transmission link.

Abstract: A method for calibrating an image sensor having multiple outputs, the method includes the steps of capturing an image on the image sensor, injecting one or more substantially identical pairs of signals into corresponding portions of the captured image, reading out the captured image with the injected signals into two or more outputs, and comparing two substantially identical signals from corresponding portions of the image, which comparison is used for calibrating the image.

Abstract: A CMOS active pixel sensor (APS) cell structure having dual workfunction transfer gate device and method of fabrication. The transfer gate device comprises a dielectric layer formed on a substrate and a dual workfunction gate conductor layer formed on the dielectric layer comprising a first conductivity type doped region and an abutting second conductivity type doped region. The transfer gate device defines a channel region where charge accumulated by a photosensing device is transferred to a diffusion region. A silicide structure is formed atop the dual workfunction gate conductor layer for electrically coupling the first and second conductivity type doped regions. In one embodiment, the silicide contact is smaller in area dimension than an area dimension of said dual workfunction gate conductor layer. Presence of the silicide strap prevents the diodic behavior from allowing one or the other side of the gate to float to an indeterminate voltage.

Abstract: Systems and methods by which voice/data communications may occur in multiple modes/protocols are disclosed. In particular, systems and methods are provided for multiple native mode/protocol voice and data transmissions and receptions with a computing system having a multi-bus structure, including, for example, a TDM bus and a packet bus, and multi-protocol framing engines. Such systems preferably include subsystem functions such as PBX, voice mail and other telephony functions, LAN hub and data router. In preferred embodiments, a TDM bus and a packet bus are intelligently bridged and managed, thereby enabling such multiple mode/protocol voice and data transmissions to be intelligently managed and controlled with a single, integrated system. A computer or other processor includes a local area network controller, which provides routing and hub(s) for one or more packet networks. The computer also is coupled to a buffer/framer, which serves to frame/deframe data to/from the computer from TDM bus.

Abstract: Systems and methods by which voice/data communications may occur in multiple modes/protocols are disclosed. In particular, systems and methods are provided for multiple native mode/protocol voice and data transmissions and receptions with a computing system having a multi-bus structures including, for example, a TDM bus and a packet bus, and multi-protocol framing engines. Such systems preferably include subsystem functions such as PBX, voice mail and other telephony functions, LAN hub and data router. In preferred embodiments, a TDM bus and a packet bus are intelligently bridged and managed, thereby enabling such multiple mode/protocol voice and data transmissions to be intelligently managed and controlled with a single, integrated system. A computer or other processor includes a local area network controller, which provides routing and hub(s) for one or more packet networks. The computer also is coupled to a buffer/framer, which serves to frame/deframe data to/from the computer from TDM bus.

Abstract: A charge-coupled device having an improved charge-transfer efficiency over a broad temperature range.

Abstract: A charge coupled device having a layer of a semiconductor material on a surface of a substrate body of a semiconductor material. The layer is of a material which can be epitaxially deposited on the body with good crystalline quality. The material of the layer has a conduction band and/or valence band which is different from that of the body so as to provide a discontinuity in the energy level of the conduction band and/or valence band at the junction of the layer and the body during the operation of the charge coupled device. At least one electrode is over and insulated from the layer. The discontinuity in the conduction band and/or valence band creates a well in which photogenerated charge is collected.

Abstract: An interline transfer type area image sensor which operates in a non-interlaced mode and has an array of columns and rows of photoreceptor in which charge from each pixel is transferred into a stage of a vertical two-phase CCD shift register formed by adjacent electrodes of the CCD. Each electrode of a stage has a separate voltage clock. An ion implanted vertical transfer barrier region is formed under an edge of each electrode.

Abstract: A high-gain, low-noise transistor amplifier comprises an input, an output, and first and second field effect transistors each having a gate, a drain, and a source and being formed in a common semiconductor substrate. The second transistor is a depletion mode transistor if it is of the same conductivity type as the first but is an enhancement mode transistor if it is of opposite conductivity type with respect to the first. In an amplifier configuration, the input is coupled to the gate of the first transistor, the source of the first transistor is coupled to the gate of the second transistor, the source of the second transistor is coupled to the output, and there is a direct-coupled feedback path from the source of the second transistor to the drain of the first transistor. At least the first transistor is formed in an isolated well of conductivity opposite to that of the substrate in the semiconductor substrate and its source is coupled directly to that well.

Abstract: An image sensor formed on a P-type substrate includes a plurality of pinned diode photodiodes, a CCD shift register and a separate buried transfer gate located between each of the photodiodes and the CCD shift register. The photodetectors are arranged in at least one line. The CCD shift register extends along the line of photodetectors. Each of the pinned diode photodetectors includes a first region of N-type conductivity in the substrate and a second region of P+ type conductivity in the first region and along the substrate surface. The CCD shift register includes a channel region of N-type conductivity in the substrate surface and two sets of conductive gates along the channel region and insulated from the substrate surface. Each transfer gate includes a transfer channel region of N-type conductivity in the substrate and extending along the substrate surface from the shift register channel region to the first region of its respective photodetector.

Abstract: In interline transfer type image sensing devices, photogenerated charge is transferred from a collection node into a charge coupled shift register. The framing rate of these detectors is typically limited by the maximum readout rate of the shift register. A CCD image sensing device with multiple shift register outputs for higher framing rate, utilizes alternating shift register orientations and multiplexing of multiple shift registers to a each output in order to match the pitches of the detector columns and output bondpads. This configuration allows detectors of different size to be made more easily. This detector additionally uses a combination of low-lag photodiodes, low transfer inefficiency true two-phase charge coupled shift registers, and low noise charge sensing amplifiers to provide non-interlaced readout of the image with minimum signal loss and noise while operating at high frame rates.