Patents by Inventor Edward Wolff
Edward Wolff has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090063724Abstract: Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized test cases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified.Type: ApplicationFiled: July 12, 2007Publication date: March 5, 2009Inventors: Gerald G. Pechanek, David Carl Strube, Edwin Frank Barry, Charles W. Kurak, JR., Carl Donald Busboom, Dale Edward Schneider, Nikos P. Pitsianis, Grayson Morris, Edward A. Wolff, Patrick R. Marchand, Ricardo E. Rodriguez, Marco C. Jacobs
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Publication number: 20090019269Abstract: Techniques for performing a bit rake instruction in a programmable processor. The bit rake instruction extracts an arbitrary pattern of bits from a source register, based on a mask provided in another register, and packs and right justifies the bits into a target register. The bit rake instruction allows any set of bits from the source register to be packed together.Type: ApplicationFiled: September 29, 2008Publication date: January 15, 2009Applicant: Altera CorporationInventors: Edward A. Wolff, Peter R. Molnar, Ayman Elezabi, Gerald George Pechanek
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Publication number: 20080235496Abstract: A scalable reconfigurable register file (SRRF) containing multiple register files, read and write multiplexer complexes, and a control unit operating in response to instructions is described. Multiple address configurations of the register files are supported by each instruction and different configurations are operable simultaneously during a single instruction execution. For example, with separate files of the size 32×32 supported configurations of 128×32 bit s, 64x64 bit s and 32×128 bit s can be in operation each cycle. Single width, double width, quad width operands are optimally supported without increasing the register file size and without increasing the number of register file read or write ports.Type: ApplicationFiled: June 3, 2008Publication date: September 25, 2008Applicant: Altera CorporationInventors: Gerald George Pechanek, Edward A. Wolff
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Patent number: 7398347Abstract: A scalable reconfigurable register file (SRRF) containing multiple register files, read and write multiplexer complexes, and a control unit operating in response to instructions is described. Multiple address configurations of the register files are supported by each instruction and different configurations are operable simultaneously during a single instruction execution. For example, with separate files of the size 32×32 supported configurations of 128×32 bit s, 64×64 bit s and 32×128 bit s can be in operation each cycle. Single width, double width, quad width operands are optimally supported without increasing the register file size and without increasing the number of register file read or write ports.Type: GrantFiled: July 14, 2004Date of Patent: July 8, 2008Assignee: Altera CorporationInventors: Gerald George Pechanek, Edward A. Wolff
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Publication number: 20080133892Abstract: Techniques for adding more complex instructions and their attendant multi-cycle execution units with a single instruction multiple data stream (SIMD) very long instruction word (VLIW) processing framework are described. In one aspect, an initiation mechanism also acts as a resynchronization mechanism to read the results of multi-cycle execution. This multi-purpose mechanism operates with a short instruction word (SIW) issue of the multi-cycle instruction, in a sequence processor (SP) alone, with a VLIW, and across all processing elements (PEs) individually or as an array of PEs. A number of advantageous floating point instructions are also described.Type: ApplicationFiled: July 16, 2007Publication date: June 5, 2008Applicant: ALTERA CORPORATIONInventors: Gerald G. Pechanek, David Carl Strube, Edward A. Wolff, Edwin Frank Barry, Grayson Morris, Carl Donald Busboom, Dale Edward Schneider
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Publication number: 20080120494Abstract: Low power architecture features and techniques are provided in a scalable array indirect VLIW processor. These features and techniques include power control of a reconfigurable register file, conditional power control of multi-cycle operations and indirect VLIW utilization, and power control of VLIW-based vector processing using the ManArray register file indexing mechanism. These techniques are applicable to all processing elements (PEs) and the array controller sequence processor (SP) to provide substantial power savings.Type: ApplicationFiled: January 29, 2008Publication date: May 22, 2008Applicant: Altera CorporationInventors: Patrick Marchand, Gerald Pechanek, Edward Wolff
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Publication number: 20080059663Abstract: A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing transfer engine supporting multiple transfer controllers which may work independently or in cooperation to carry out data transfers, with each transfer controller acting as an autonomous processor, fetching and dispatching DMA instructions to multiple execution units. In particular, mechanisms for initiating and controlling the sequence of data transfers are provided, as are processes for autonomously fetching DMA instructions which are decoded sequentially but executed in parallel.Type: ApplicationFiled: July 30, 2007Publication date: March 6, 2008Applicant: Altera CorporationInventors: Edwin Barry, Edward Wolff
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Patent number: 7302504Abstract: A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing transfer engine supporting multiple transfer controllers which may work independently or in cooperation to carry out data transfers, with each transfer controller acting as an autonomous processor, fetching and dispatching DMA instructions to multiple execution units. In particular, mechanisms for initiating and controlling the sequence of data transfers are provided, as are processes for autonomously fetching DMA instructions which are decoded sequentially but executed in parallel.Type: GrantFiled: September 21, 2006Date of Patent: November 27, 2007Assignee: Altera CorporationInventors: Edwin Franklin Barry, Edward A. Wolff
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Patent number: 7266620Abstract: A system core having an internal memory which transfers data from an external device to the internal memory is described. To this end, the system core includes a processor, a direct memory access (DMA) controller, an instruction memory and a plurality of memories. The instruction memory contains processor instructions and DMA instructions. The DMA controller fetches DMA instructions from the instruction memory. The DMA controller executes the fetched DMA instructions and thus populates the plurality of memories with data from the external device. The processor then operates on the data found in the populated memories.Type: GrantFiled: March 10, 2004Date of Patent: September 4, 2007Assignee: Altera CorporationInventors: Gerald George Pechanek, David Strube, Edwin Franklin Barry, Charles W. Kurak, Jr., Carl Donald Busboom, Dale Edward Schneider, Nikos P. Pitsianis, Grayson Morris, Edward A. Wolff, Patrick R. Marchand, Ricardo E. Rodriguez, Marco C. Jacobs
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Patent number: 7263624Abstract: Low power architecture features and techniques are provided in a scalable array indirect VLIW processor. These features and techniques include power control of a reconfigurable register file, conditional power control of multi-cycle operations and indirect VLIW utilization, and power control of VLIW-based vector processing using the ManArray register file indexing mechanism. These techniques are applicable to all processing elements (PEs) and the array controller sequence processor (SP) to provide substantial power savings.Type: GrantFiled: May 13, 2005Date of Patent: August 28, 2007Assignee: Altera CorporationInventors: Patrick R. Marchand, Gerald George Pechanek, Edward A. Wolff
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Patent number: 7257696Abstract: Techniques for adding more complex instructions and their attendant multi-cycle execution units with a single instruction multiple data stream (SIMD) very long instruction word (VLIW) processing framework are described. In one aspect, an initiation mechanism also acts as a resynchronization mechanism to read the results of multi-cycle execution. This multi-purpose mechanism operates with a short instruction word (SIW) issue of the multi-cycle instruction, in a sequence processor (SP) alone, with a VLIW, and across all processing elements (PEs) individually or as an array of PEs. A number of advantageous floating point instructions are also described.Type: GrantFiled: August 15, 2003Date of Patent: August 14, 2007Assignee: Altera CorporationInventors: Gerald George Pechanek, David Strube, Edward A. Wolff, Edwin Franklin Barry, Grayson Morris, Carl Donald Busboom, Dale Edward Schneider
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Publication number: 20070088868Abstract: A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing transfer engine supporting multiple transfer controllers which may work independently or in cooperation to carry out data transfers, with each transfer controller acting as an autonomous processor, fetching and dispatching DMA instructions to multiple execution units. In particular, mechanisms for initiating and controlling the sequence of data transfers are provided, as are processes for autonomously fetching DMA instructions which are decoded sequentially but executed in parallel.Type: ApplicationFiled: September 21, 2006Publication date: April 19, 2007Applicant: Altera CorporationInventors: Edwin Barry, Edward Wolff
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Patent number: 7130934Abstract: A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing transfer engine supporting multiple transfer controllers which may work independently or in cooperation to carry out data transfers, with each transfer controller acting as an autonomous processor, fetching and dispatching DMA instructions to multiple execution units. In particular, mechanisms for initiating and controlling the sequence of data transfers are provided, as are processes for autonomously fetching DMA instructions which are decoded sequentially but executed in parallel.Type: GrantFiled: April 7, 2005Date of Patent: October 31, 2006Assignee: Altera CorporationInventors: Edwin Franklin Barry, Edward A. Wolff
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Patent number: 7024540Abstract: Port priorities are defined on a 32-bit word, 16-bit half-word, and 8-bit byte basis to control the write enable signals to a compute register file (CRF). With a manifold array (ManArray) reconfigurable register file, it is possible to have double-word 64-bit and single word 32-bit data-type instructions mixed with other double-word, single-word, half-word, or byte data-type instructions within the same very long instruction word (VLIW). By resolving a write priority conflict on the byte, half-word, or word that is in conflict during the VLIW execution, it is possible to have partial operations complete that provide a useful function. For example, a load half-word to the half-word H0 portion of a 32-bit register R0 can have priority to complete its operation while a 64-bit shift of the register pair R0 and R1 will complete its operation on the non-conflicting half-word portions of the 64-bit register R0 and R1.Type: GrantFiled: October 28, 2003Date of Patent: April 4, 2006Assignee: PTS CorporationInventors: Edwin Frank Barry, Edward A. Wolff, Patrick Rene Marchand, David Carl Strube
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Publication number: 20060024140Abstract: The present disclosure provides a removable tap chaser for tapping an internal thread in a hole in a workpiece. The tap chaser consists of at least one carbide material and is adapted to be removably mounted on a tap system such as, for example, one of a collapsible tap system and a non-collapsible tap system.Type: ApplicationFiled: July 30, 2004Publication date: February 2, 2006Inventors: Edward Wolff, Donald Barnes, V. Shook
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Patent number: 6965991Abstract: A reconfigurable register file system is described. The reconfigurable register file system includes an instruction register for storing an instruction specifying an operational requirement, a reconfigurable register file comprising an odd register file having at least one data read port, and an even register file having at least one data read port. The reconfigurable register file system may further suitably include an execution unit connected to the data read ports of the odd and even register files and port usage control logic connected to the instruction register and the reconfigurable register file to control the odd register file and the even register file port address input so that data read port lines change only as needed to support the operational requirement specified by the instruction.Type: GrantFiled: January 11, 2005Date of Patent: November 15, 2005Assignee: PTS CorporationInventors: Patrick R. Marchand, Gerald G. Pechanek, Edward A. Wolff
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Publication number: 20050223253Abstract: Low power architecture features and techniques are provided in a scalable array indirect VLIW processor. These features and techniques include power control of a reconfigurable register file, conditional power control of multi-cycle operations and indirect VLIW utilization, and power control of VLIW-based vector processing using the ManArray register file indexing mechanism. These techniques are applicable to all processing elements (PEs) and the array controller sequence processor (SP) to provide substantial power savings.Type: ApplicationFiled: May 13, 2005Publication date: October 6, 2005Applicant: PTS CorporationInventors: Patrick Marchand, Gerald Pechanek, Edward Wolff
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Patent number: 6944683Abstract: A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing transfer engine supporting multiple transfer controllers which may work independently or in cooperation to carry out data transfers, with each transfer controller acting as an autonomous processor, fetching and dispatching DMA instructions to multiple execution units. In particular, mechanisms for initiating and controlling the sequence of data transfers are provided, as are processes for autonomously fetching DMA instructions which are decoded sequentially but executed in parallel.Type: GrantFiled: February 19, 2004Date of Patent: September 13, 2005Assignee: PTS CorporationInventors: Edwin Frank Barry, Edward A. Wolff
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Publication number: 20050172050Abstract: A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing transfer engine supporting multiple transfer controllers which may work independently or in cooperation to carry out data transfers, with each transfer controller acting as an autonomous processor, fetching and dispatching DMA instructions to multiple execution units. In particular, mechanisms for initiating and controlling the sequence of data transfers are provided, as are processes for autonomously fetching DMA instructions which are decoded sequentially but executed in parallel.Type: ApplicationFiled: April 7, 2005Publication date: August 4, 2005Applicant: PTS CorporationInventors: Edwin Barry, Edward Wolff
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Patent number: 6912608Abstract: Techniques for a pipelined bus which provides a very high performance interface to computing elements, such as processing elements, host interfaces, memory controllers, and other application-specific coprocessors and external interface units. The pipelined bus is a robust interconnected bus employing a scalable, pipelined, multi-client topology, with a fully synchronous, packet-switched, split-transaction data transfer model. Multiple non-interfering transfers may occur concurrently since there is no single point of contention on the bus. An aggressive packet transfer model with local conflict resolution in each client and packet-level retries allows recovery from collisions and buffer backups. Clients are assigned unique IDs, based upon a mapping from the system address space allowing identification needed for quick routing of packets among clients.Type: GrantFiled: April 25, 2002Date of Patent: June 28, 2005Assignee: PTS CorporationInventors: Edward A. Wolff, David Baker, Bryan Garnett Cope, Edwin Franklin Barry