Patents by Inventor Edward Wolff
Edward Wolff has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6845445Abstract: Low power architecture features and techniques are provided in a scalable array indirect VLIW processor. These features and techniques include power control of a reconfigurable register file, conditional power control of multi-cycle operations and indirect VLIW utilization, and power control of VLIW-based vector processing using the ManArray register file indexing mechanism. These techniques are applicable to all processing elements (PEs) and the array controller sequence processor (SP) to provide substantial power savings.Type: GrantFiled: May 11, 2001Date of Patent: January 18, 2005Assignee: PTS CorporationInventors: Patrick R. Marchand, Gerald G. Pechanek, Edward A. Wolff
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Patent number: 6795909Abstract: Processing element to processing element switch connection control is described using a receive model that precludes communication hazards from occurring in a synchronous MIMD mode of operation. Such control allows different communication topologies and various processing effects such as an array transpose, hypercomplement or the like to be efficiently achieved utilizing architectures, such as the manifold array processing architecture. An encoded instruction method reduces the amount of state information and setup burden on the programmer taking advantage of the recognition that the majority of algorithms will use only a small fraction of all possible mux settings available. Thus, by means of transforming the PE identification based upon a communication path specified by a PE communication instruction an efficient switch control mechanism can be used.Type: GrantFiled: April 1, 2002Date of Patent: September 21, 2004Assignee: PTS CorporationInventors: Edwin F. Barry, Gerald G. Pechanek, Thomas L. Drabenstott, Edward A. Wolff, Nikos P. Pitsianis, Grayson Morris
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Publication number: 20040162925Abstract: A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing transfer engine supporting multiple transfer controllers which may work independently or in cooperation to carry out data transfers, with each transfer controller acting as an autonomous processor, fetching and dispatching DMA instructions to multiple execution units. In particular, mechanisms for initiating and controlling the sequence of data transfers are provided, as are processes for autonomously fetching DMA instructions which are decoded sequentially but executed in parallel.Type: ApplicationFiled: February 19, 2004Publication date: August 19, 2004Applicant: PTS CorporationInventors: Edwin Franklin Barry, Edward A. Wolff
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Patent number: 6748517Abstract: Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized testcases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified.Type: GrantFiled: June 22, 2000Date of Patent: June 8, 2004Assignee: PTS CorporationInventors: Gerald G. Pechanek, David Carl Strube, Edwin Frank Barry, Charles W. Kurak, Jr., Carl Donald Busboom, Dale Edward Schneider, Nikos P. Pitsianis, Grayson Morris, Edward A. Wolff, Patrick R. Marchand, Ricardo E. Rodriguez, Marco C. Jacobs
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Publication number: 20040093484Abstract: Port priorities are defined on a 32-bit word, 16-bit half-word, and 8-bit byte basis to control the write enable signals to a compute register file (CRF). With a manifold array (ManArray) reconfigurable register file, it is possible to have double-word 64-bit and single word 32-bit data-type instructions mixed with other double-word, single-word, half-word, or byte data-type instructions within the same very long instruction word (VLIW). By resolving a write priority conflict on the byte, half-word, or word that is in conflict during the VLIW execution, it is possible to have partial operations complete that provide a useful function. For example, a load half-word to the half-word H0 portion of a 32-bit register R0 can have priority to complete its operation while a 64-bit shift of the register pair R0 and R1 will complete its operation on the non-conflicting half-word portions of the 64-bit register R0 and R1.Type: ApplicationFiled: October 28, 2003Publication date: May 13, 2004Applicant: PTS CorporationInventors: Edwin Frank Barry, Edward A. Wolff, Patrick Rene Marchand, David Carl Strube
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Patent number: 6721822Abstract: A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing transfer engine supporting multiple transfer controllers which may work independently or in cooperation to carry out data transfers, with each transfer controller acting as an autonomous processor, fetching and dispatching DMA instructions to multiple execution units. In particular, mechanisms for initiating and controlling the sequence of data transfers are provided, as are processes for autonomously fetching DMA instructions which are decoded sequentially but executed in parallel.Type: GrantFiled: September 24, 2002Date of Patent: April 13, 2004Assignee: PTS CorporationInventors: Edwin Frank Barry, Edward A. Wolff
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Publication number: 20040054871Abstract: Techniques for adding more complex instructions and their attendant multi-cycle execution units with a single instruction multiple data stream (SIMD) very long instruction word (VLIW) processing framework are described. In one aspect, an initiation mechanism also acts as a resynchronization mechanism to read the results of multi-cycle execution. This multi-purpose mechanism operates with a short instruction word (SIW) issue of the multi-cycle instruction, in a sequence processor (SP) alone, with a VLIW, and across all processing elements (PEs) individually or as an array of PEs. A number of advantageous floating point instructions are also described.Type: ApplicationFiled: August 15, 2003Publication date: March 18, 2004Applicant: PTS CorporationInventors: Gerald George Pechanek, David Carl Strube, Edward A. Wolff, Edwin Franklin Barry, Grayson Morris, Carl Donald Busboom, Dale Edward Schneider
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Patent number: 6654870Abstract: Port priorities are defined on a 32-bit word, 16-bit half-word, and 8-bit byte basis to control the write enable signals to a compute register file (CRF). With a manifold array (ManArray) reconfigurable register file, it is possible to have double-word 64-bit and single word 32-bit data-type instructions mixed with other double-word, single-word, half-word, or byte data-type instructions within the same very long instruction word (VLIW). By resolving a write priority conflict on the byte, half-word, or word that is in conflict during the VLIW execution, it is possible to have partial operations complete that provide a useful function. For. example, a load half-word to the half-word H0 portion of a 32-bit register R0 can have priority to complete its operation while a 64-bit shift of the register pair R0 and R1 will complete its operation on the non-conflicting half-word portions of the 64-bit register R0 and R1.Type: GrantFiled: June 21, 2000Date of Patent: November 25, 2003Assignee: PTS CorporationInventors: Edwin Frank Barry, Edward A. Wolff, Patrick Rene Marchand, David Carl Strube
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Patent number: 6622234Abstract: Techniques for adding more complex instructions and their attendant multi-cycle execution units with a single instruction multiple data, stream (SIMD) very long instruction word (VLIW) processing framework are described. In one aspect, an initiation mechanism also acts as a resynchronization mechanism to read the results of multi-cycle execution. This multi-purpose mechanism operates with a short instruction word (SIW) issue of the multi-cycle instruction, in a sequence processor (SP) alone, with a VLIW, and across all processing elements (PEs) individually or as an array of PEs. A number of advantageous floating point instructions are also described.Type: GrantFiled: June 21, 2000Date of Patent: September 16, 2003Assignee: PTS CorporationInventors: Gerald G. Pechanek, David Carl Strube, Edward A. Wolff, Edwin Frank Barry, Grayson Morris, Carl Donald Busboom, Dale Edward Schneider
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Publication number: 20030105945Abstract: Techniques for performing a bit rake instruction in a programmable processor. The bit rake instruction extracts an arbitrary pattern of bits from a source register, based on a mask provided in another register, and packs and right justifies the bits into a target register. The bit rake instruction allows any set of bits from the source register to be packed together.Type: ApplicationFiled: October 29, 2002Publication date: June 5, 2003Applicant: BOPS, Inc.Inventors: Edward A. Wolff, Peter R. Molnar, Ayman Elezabi, Gerald George Pechanek
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Publication number: 20030079065Abstract: A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing transfer engine supporting multiple transfer controllers which may work independently or in cooperation to carry out data transfers, with each transfer controller acting as an autonomous processor, fetching and dispatching DMA instructions to multiple execution units. In particular, mechanisms for initiating and controlling the sequence of data transfers are provided, as are processes for autonomously fetching DMA instructions which are decoded sequentially but executed in parallel.Type: ApplicationFiled: September 24, 2002Publication date: April 24, 2003Inventors: Edwin Frank Barry, Edward A. Wolff
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Publication number: 20030046462Abstract: Techniques for a pipelined bus which provides a very high performance interface to computing elements, such as processing elements, host interfaces, memory controllers, and other application-specific coprocessors and external interface units. The pipelined bus is a robust interconnected bus employing a scalable, pipelined, multi-client topology, with a fully synchronous, packet-switched, split-transaction data transfer model. Multiple non-interfering transfers may occur concurrently since there is no single point of contention on the bus. An aggressive packet transfer model with local conflict resolution in each client and packet-level retries allows recovery from collisions and buffer backups. Clients are assigned unique IDs, based upon a mapping from the system address space allowing identification needed for quick routing of packets among clients.Type: ApplicationFiled: April 25, 2002Publication date: March 6, 2003Applicant: BOPS, Inc.Inventors: Edward A. Wolff, David Baker, Bryan Garnett Cope, Edwin Franklin Barry
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Publication number: 20020144082Abstract: Processing element to processing element switch connection control is described using a receive model that precludes communication hazards from occurring in a synchronous MIMD mode of operation. Such control allows different communication topologies and various processing effects such as an array transpose, hypercomplement or the like to be efficiently achieved utilizing architectures, such as the manifold array processing architecture. An encoded instruction method reduces the amount of state information and setup burden on the programmer taking advantage of the recognition that the majority of algorithms will use only a small fraction of all possible mux settings available. Thus, by means of transforming the PE identification based upon a communication path specified by a PE communication instruction an efficient switch control mechanism can be used.Type: ApplicationFiled: April 1, 2002Publication date: October 3, 2002Applicant: BOPS, Inc.Inventors: Edwin Franklin Barry, Gerald George Pechanek, Thomas L. Drabenstott, Edward A. Wolff, Nikos P. Pitsianis, Grayson Morris
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Patent number: 6457073Abstract: A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing transfer engine supporting multiple transfer controllers which may work independently or in cooperation to carry out data transfers, with each transfer controller acting as an autonomous processor, fetching and dispatching DMA instructions to multiple execution units. In particular, mechanisms for initiating and controlling the sequence of data transfers are provided, as are processes for autonomously fetching DMA instructions which are decoded sequentially but executed in parallel.Type: GrantFiled: June 29, 2001Date of Patent: September 24, 2002Assignee: Bops, Inc.Inventors: Edwin Frank Barry, Edward A. Wolff
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Patent number: 6366997Abstract: Processing element to processing element switch connection control is described using a receive model that precludes communication hazards from occurring in a synchronous MIMD mode of operation. Such control allows different communication topologies and various processing effects such as an array transpose, hypercomplement or the like to be efficiently achieved utilizing architectures, such as the manifold array processing architecture. An encoded instruction method reduces the amount of state information and setup burden on the programmer taking advantage of the recognition that the majority of algorithms will use only a small fraction of all possible mux settings available. Thus, by means of transforming the PE identification based upon a communication path specified by a PE communication instruction an efficient switch control mechanism can be used.Type: GrantFiled: August 29, 2000Date of Patent: April 2, 2002Assignee: BOPS, Inc.Inventors: Edwin F. Barry, Gerald G. Pechanek, Thomas L. Drabenstott, Edward A. Wolff, Nikos P. Pitsianis, Grayson Morris
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Publication number: 20020010814Abstract: A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing transfer engine supporting multiple transfer controllers which may work independently or in cooperation to carry out data transfers, with each transfer controller acting as an autonomous processor, fetching and dispatching DMA instructions to multiple execution units. In particular, mechanisms for initiating and controlling the sequence of data transfers are provided, as are processes for autonomously fetching DMA instructions which are decoded sequentially but executed in parallel.Type: ApplicationFiled: June 29, 2001Publication date: January 24, 2002Inventors: Edwin Frank Barry, Edward A. Wolff
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Publication number: 20020004916Abstract: Low power architecture features and techniques are provided in a scalable array indirect VLIW processor. These features and techniques include power control of a reconfigurable register file, conditional power control of multi-cycle operations and indirect VLIW utilization, and power control of VLIW-based vector processing using the ManArray register file indexing mechanism. These techniques are applicable to all processing elements (PEs) and the array controller sequence processor (SP) to provide substantial power savings.Type: ApplicationFiled: May 11, 2001Publication date: January 10, 2002Inventors: Patrick R. Marchand, Gerald G. Pechanek, Edward A. Wolff
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Patent number: 6260082Abstract: A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing transfer engine supporting multiple transfer controllers which may work independently or in cooperation to carry out data transfers, with each transfer controller acting as an autonomous processor, fetching and dispatching DMA instructions to multiple execution units. In particular, mechanisms for initiating and controlling the sequence of data transfers are provided, as are processes for autonomously fetching DMA instructions which are decoded sequentially but executed in parallel.Type: GrantFiled: December 23, 1999Date of Patent: July 10, 2001Assignee: Bops, Inc.Inventors: Edwin Frank Barry, Edward A. Wolff
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Patent number: 6167501Abstract: Processing element to processing element switch connection control is described using a receive model that precludes communication hazards from occurring in a synchronous MIMD mode of operation. Such control allows different communication topologies and various processing effects such as an array transpose, hypercomplement or the like to be efficiently achieved utilizing architectures, such as the manifold array processing architecture. An encoded instruction method reduces the amount of state information and setup burden on the programmer taking advantage of the recognition that the majority of algorithms will use only a small fraction of all possible mux settings available. Thus, by means of transforming the PE identification based upon a communication path specified by a PE communication instruction an efficient switch control mechanism can be used.Type: GrantFiled: October 9, 1998Date of Patent: December 26, 2000Assignee: Billions of Operations Per Second, Inc.Inventors: Edwin F. Barry, Gerald G. Pechanek, Thomas L. Drabenstott, Edward A. Wolff, Nikos P. Pitsianis, Grayson Morris
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Patent number: 4527237Abstract: A data processing system comprising an active and intelligent main store including a main memory, a main store controller for accessing the main memory in a manner allowing different address and data structures, and a main store bus connected to the controller. At least one processor of a first type is connected to the main store bus, this being an auxiliary processor for performing input-output and other operations. At least one processor of a second type also is connected to the main store bus, this being an execution processor for fetching, decoding and executing instructions. All or some of either or both of the auxiliary processors and execution processors may be different. A supervisory processor for initiating configuring and monitoring the system is connected to the main store bus. A communication bus is connected to the processors of the first and second types and to the supervisory processor. A diagnostic bus connects the supervisory processor to each of the processors of the first and second types.Type: GrantFiled: April 14, 1983Date of Patent: July 2, 1985Assignee: Nanodata Computer CorporationInventors: Gideon Frieder, David T. Hughes, Mark H. Kline, John T. Liebel, Jr., David P. Meier, Edward A. Wolff