Abstract: A phase-locked loop (PLL) is disclosed. One embodiment, among others, includes a PLL that provides a control signal and a square root module configured to receive state information, the state information corresponding to tuning information, the square root module further configured to multiply the control signal by a square root of the state information to provide a tuning signal.

Abstract: According to one exemplary embodiment, a digitally controlled oscillator includes a capacitive tuning network, where the capacitive tuning network controls a frequency of an output signal of the digitally controlled oscillator. The capacitive tuning network includes a switched capacitor array, where a change of a first capacitance of the switched capacitor array causes the capacitive tuning network to change by a second capacitance, and where the first capacitance is larger than the second capacitance. According to this exemplary embodiment, the capacitive tuning network further includes a first capacitor coupled in parallel with the switched capacitor array. The first capacitor has a third capacitance, which is larger than the first capacitance. The capacitive tuning network further includes a second capacitor coupled in series with the first capacitor and the switched capacitor array. The second capacitor can have a fourth capacitance, where the third capacitance is larger than the fourth capacitance.

Abstract: A mixer is disclosed having an output stage with an amplifier or gain device configured in a feedback loop to maintain a virtual ground at the input to the gain device. The gain device provides significant dynamic range, gain, and the appropriate impedance matching to insure a low noise output signal of a desired magnitude. Use of an amplifying output stage removes the dependence between mixer gain and mixer configuration, such as mixer bias resistor value, while concurrently overcome undesirable flicker noise that results from use of active devices in the mixer bias structure. A stable virtual ground at the mixer output and gain device input provides linearity over frequency.

Abstract: To reduce the size and cost of a loop filter, such as for example a loop filter in a phase lock loop, two or more charge pumps may be configured to inject current into two or more nodes of the loop filter. In such a configuration and for a given voltage value across the loop filter, capacitors sizes may be minimized and loop stability may be maximized. Current injection at the nodes of the loop filter increases voltage across the loop filter without a corresponding increase in capacitor size. In one embodiment the feedback loop comprises a phase or frequency detector configured to compare a feedback signal with a reference signal and based on the comparison, output or cause to be output one or more current signals to a loop filter. The current injection to the loop filter generates a voltage, which may be detected to generate a corresponding output signal.

Abstract: A phase-locked loop (PLL) is disclosed. One embodiment, among others, includes a PLL that provides a control current and varies the control current in proportion to an inverse of N squared. N is the ratio of the output frequency of the PLL system to the reference frequency of the PLL system. The varying of the control current compensates for bandwidth changes of the PLL system.

Abstract: A phase-locked loop and method are disclosed. One method embodiment includes providing a dual-path filter of a phase-locked loop, the dual-path filter consisting of passive components, and summing control signals in the dual-path filter using the passive components.

Abstract: A phase-locked loop and method of operation are disclosed. One embodiment includes providing a phase-locked loop, comprising a charge pump system comprising a first charge pump and a second charge pump, the charge pump system configured to provide control signals, a dual path filter, the dual path filter consisting of passive components that are configured to provide summation of control signals, wherein the dual path filter includes a first node coupled between a first charge pump and a first capacitor, wherein the dual path filter includes a second node coupled to a second charge pump through a first resistor, wherein the second node is connected to the first capacitor, and a voltage source coupled to the second node through a second resistor.

Abstract: According to one exemplary embodiment, a digitally controlled oscillator includes a capacitive tuning network, where the capacitive tuning network controls a frequency of an output signal of the digitally controlled oscillator. The capacitive tuning network includes a switched capacitor array, where a change of a first capacitance of the switched capacitor array causes the capacitive tuning network to change by a second capacitance, and where the first capacitance is larger than the second capacitance. According to this exemplary embodiment, the capacitive tuning network further includes a first capacitor coupled in parallel with the switched capacitor array. The first capacitor has a third capacitance, which is larger than the first capacitance. The capacitive tuning network further includes a second capacitor coupled in series with the first capacitor and the switched capacitor array. The second capacitor can have a fourth capacitance, where the third capacitance is larger than the fourth capacitance.

Abstract: A phase-locked loop (PLL) is disclosed. One embodiment, among others, includes a PLL that provides a control signal and a square root module configured to receive state information, the state information corresponding to tuning information, the square root module further configured to multiply the control signal by a square root of the state information to provide a tuning signal.

Abstract: A phase-locked loop and method are disclosed. One method embodiment includes providing a dual path filter of a phase-locked loop, the dual path filter consisting of passive components, and summing control signals in the dual path filter using the passive components.

Abstract: A phase-locked loop (PLL) is disclosed. One embodiment, among others, includes a PLL that provides a control current and varies the control current in proportion to an inverse of N squared. N is the ratio of the output frequency of the PLL system to the reference frequency of the PLL system. The varying of the control current compensates for bandwidth changes of the PLL system.