Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.

Abstract: Semiconductor devices and methods are provided. For example, a semiconductor device includes a plurality of semiconductor fins patterned in a starting semiconductor substrate; a set of gate structures formed on the starting semiconductor substrate; a set of spacers formed around each of the set of gate structures; a source and drain region grown around the plurality of semiconductor fins; a conductive metal material on the source and drain region, an insulating material disposed over an upper surface of the conductive metal material and the gate structure; and a plurality of metal contacts in the insulator material. The bottom surface of the plurality of metal contacts is in contact with at least a portion of an upper surface of the gate structure and at least a portion of an upper surface of the conductive metal material.

Abstract: An advanced security method for verifying that integrated circuit patterns being processed into one or more layers provided to a wafer are trusted patterns and that the wafer being used during processing is a trusted wafer is provided. The method includes separate steps of pattern verification and wafer verification. Notably, the method includes first verifying that a pattern printed on a wafer matches a pattern of a trusted reference. Next, a peak and valley profile present at a specific location on a backside surface of the wafer is measured. The method further includes second verify that the measured peak and valley profile matches an original peak and valley profile measured at the same location on the backside surface of the wafer.

Abstract: The present invention provides 3D stack NOR devices having increased storage area. In one aspect, a method of forming a memory device includes: forming a memory stack on a wafer having alternating sacrificial word and bit line layers separated by dielectric layers; patterning a channel hole in the stack; recessing the sacrificial word line layers to form divots along opposite sides of the channel hole; selectively forming a floating gate stack in the divots; filling the channel hole and divots to form a channel; patterning the memory stack into a stair case structure; burying the memory stack in a dielectric; replacing the sacrificial word line layers in the memory stack with word line contacts; and replacing the sacrificial bit line layers in the memory stack with bit line contacts. A memory device is also provided.

Abstract: A multi-chip module includes a first semiconductor component including a first set of connections having a first pitch dimension and at least a second set of connections having a second pitch dimension, wherein the first pitch dimension is smaller than the second pitch dimension. The multi-chip module further includes a second semiconductor component interconnected with the first set of connections of the first semiconductor component. The multi-chip module further includes at least a third semiconductor component interconnected with the second set of connections of the first semiconductor component and wherein a surface of the third semiconductor component is adhered to a surface of the second semiconductor component, wherein the surfaces at least partially overlap one another.

Abstract: A method for verifying semiconductor wafers includes receiving a semiconductor wafer including a plurality of layers. A first set of measurement data is obtained for at least one layer of the plurality of layers, where the first set of measurement data includes at least one previously recorded thickness measurement for one or more portions of the at least one layer. The first set of measurement data is compared to a second set of measurement data for the at least one layer. The second set of measurement data includes at least one new thickness measurement for the one or more portions of the at least one layer. The semiconductor wafer is determined to be an authentic wafer based on the second set of measurement data corresponding to the first set of measurement data, otherwise the semiconductor is determined to not be an authentic wafer.

Abstract: Semiconductor devices include a semiconductor fin on a substrate. The semiconductor fin has channel region and source and drain regions. A gate stack is formed all around the channel region of the semiconductor fin, such that the channel region of the semiconductor fin is separated from the substrate. An interlayer dielectric is formed around the gate stack. At least a portion of the gate stack is formed in an undercut beneath the interlayer dielectric.

Abstract: Embodiments of the present invention include a tight pitch stack nanowire semiconductor device. The semiconductor device includes an active region including a blanket dielectric nanosheet. Further included are at least one fin formed on the blanket dielectric nanosheet. There is at least one gate structure formed over the at least one fin in the active region such that the blanket dielectric nanosheet forms an insulating layer between each of the at least one fin and the at least one gate structure, and a substrate such that each of the at least one fin and each of the at least one dummy gate are electrically isolated.

Abstract: The present invention provides 3D stack NOR devices having increased storage area. In one aspect, a method of forming a memory device includes: forming a memory stack on a wafer having alternating sacrificial word and bit line layers separated by dielectric layers; patterning a channel hole in the stack; recessing the sacrificial word line layers to form divots along opposite sides of the channel hole; selectively forming a floating gate stack in the divots; filling the channel hole and divots to form a channel; patterning the memory stack into a stair case structure; burying the memory stack in a dielectric; replacing the sacrificial word line layers in the memory stack with word line contacts; and replacing the sacrificial bit line layers in the memory stack with bit line contacts. A memory device is also provided.

Abstract: A method for securing and verifying semiconductor wafers during fabrication includes receiving a semiconductor wafer after a layer of features has been patterned thereon. At least one security mark is formed at one or more locations embedded within a backside of the semiconductor wafer by implanting an inert species at the one or more locations. At a subsequent point in fabrication and/or after fabrication of the semiconductor wafer has completed the backside of the wafer is inspected for detection of the at least one security mark. If the at least one security mark is not detected at an expected location within the backside of the semiconductor wafer a determination is made that the semiconductor wafer has been compromised.

Abstract: Embodiments of the invention are directed to a method of fabricating a semiconductor device. A non-limiting example of the method includes forming a fin over a substrate. The fin includes an upper fin region and a lower fin region. The lower fin region is physically coupled to the upper fin region and the substrate. A portion of the fin is removed to form a fin tunnel configured to physically separate the upper fin region from the lower fin region. A gate structure is formed and configured to fill the fin tunnel and cover a top surface, a bottom surface, a first sidewall, and a second sidewall of the upper fin region.

Abstract: A controllable resistive element and method for updating the resistance of the same includes a state device configured to provide a voltage-controlled resistance responsive to a voltage input. A battery is configured to apply a voltage to the voltage input of the state device based on a charge stored in the battery. A write device is configured to charge the battery responsive to a write signal. An erase device is configured to discharge the battery responsive to an erase signal.

Abstract: A method is presented for fine-tuning a threshold voltage of a nanosheet structure. The method includes forming a nanosheet stack over a substrate including a plurality of sacrificial layers and a plurality of nanowires, forming a sacrificial gate structure over the nanosheet stack, and partially etching one or more sacrificial layers to form cavities, the partial etching resulting in remaining sections of sacrificial layers. The method includes removing the sacrificial gate structure, removing at least one of the remaining sections of sacrificial layers to expose a surface of each of the plurality of nanowires, forming an oxidation channel on the exposed surface on only either a top side or bottom side of each of the plurality of nanowires, removing the oxidation channels to form a recess on each of the plurality of nanowires, and depositing a high-k metal gate extending into the recess of each of the plurality of nanowires.

Abstract: A method for updating the resistance of a controllable resistance element includes determining an amount of resistance change for the controllable resistive element. A charge difference for a battery is determined corresponding to the resistance change for the controllable resistive element. The battery is charged or discharged to effect the resistance change in the controllable resistive element.

Abstract: The wafer comprises a first line in a first layer of the wafer. The first line has a first terminal connected to the first line. The wafer comprises a second line in the first layer of the wafer. The second line has a second terminal connected to the second line. The second terminal has a probe connected to apply a voltage ramp. The wafer comprises a third line in the first layer of the wafer. The third line has a terminal connected to the third line.

Abstract: A method is presented for fine-tuning a threshold voltage of a nanosheet structure. The method includes forming a nanosheet stack over a substrate including a plurality of sacrificial layers and a plurality of nanowires, forming a sacrificial gate structure over the nanosheet stack, and partially etching one or more sacrificial layers to form cavities, the partial etching resulting in remaining sections of sacrificial layers. The method includes removing the sacrificial gate structure, removing at least one of the remaining sections of sacrificial layers to expose a surface of each of the plurality of nanowires, forming an oxidation channel on the exposed surface on only either a top side or bottom side of each of the plurality of nanowires, removing the oxidation channels to form a recess on each of the plurality of nanowires, and depositing a high-k metal gate extending into the recess of each of the plurality of nanowires.

Abstract: Semiconductor devices and methods of forming the same include forming a second dielectric layer on sidewalls of a channel region of a semiconductor fin. The semiconductor fin is surrounded at a fin base by a first dielectric layer. The first dielectric layer is recessed to form a gap in the channel region of the semiconductor fin between the first dielectric layer and the second dielectric layer. Material from the semiconductor fin is etched away at the gap to separate the semiconductor fin from an underlying surface in the channel region. A gate stack is formed in the channel region that completely encircles the semiconductor fin.

Abstract: A U-shaped gate dielectric structure is provided that has a horizontal gate dielectric portion having a vertical thickness, and a vertical gate dielectric wall portion extending upwards from the horizontal gate dielectric portion. The vertical gate dielectric wall portion has a lateral thickness that is greater than the vertical thickness of the horizontal gate dielectric portion. The U-shaped gate dielectric structure houses a gate conductor portion. Collectively, the U-shaped gate dielectric structure and the gate conductor portion provide a functional gate structure that has reduced capacitance.

Abstract: A method for manufacturing a 3D integrated circuit is provided. A manufacturing system provides a first integrated circuit having a first surface and a first via extending to the first surface. The manufacturing system applies a first controlled collapse chip connection (C4) solder bump to the first via. The manufacturing system provides a second integrated circuit having a second surface and a second via extending to the second surface. The manufacturing system applies a second C4 solder bump to the second via. The manufacturing system overturns the second integrated circuit onto the first integrated circuit and aligns the first C4 solder bump with the second C4 bump. The manufacturing system heats the first C4 solder bump and the second C4 solder bump until the first via contact is soldered to the second via.

Abstract: Methods for forming a tight pitch stack nanowire without shallow trench isolation including a base nanosheet formed on a substrate. At least one fin are formed, and at least one dummy gate is formed over the at least two fins, on the base nanosheet, the at least two fins including at least two alternating layers of a first material and a second material. The base nanoset is replaced with a blanket dielectric to form a shallow trench isolation (STI) around the at least one fin and around the at least one dummy gate. A gate replacement is performed to replace the at least one dummy gate and the second material with a gate conductor material and a gate cap to form gate structure.