Patents by Inventor Effendi Leobandung

Effendi Leobandung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integration of artificial intelligence devices
    Patent number: 10833010
    Abstract: Techniques that facilitate integration of artificial intelligence devices are provided. In one example, a device includes a first dual-damascene layer, a second dual-damascene layer and an artificial intelligence memory device. The first dual-damascene layer comprises a first set of copper connections formed in first dielectric material. The second dual-damascene layer that comprises a second set of copper connections formed in second dielectric material. The artificial intelligence memory device is integrated between the first dual-damascene layer and the second dual-damascene layer. A through-level via (TLV) electrical connection associated with the artificial intelligence memory device provides an interconnection between the first set of copper connections and the second set of copper connections.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hsueh-Chung Chen, Lawrence A. Clevenger, Fee Li Lie, Effendi Leobandung
  • Phase change memory
    Patent number: 10818838
    Abstract: An embodiment of the invention may include a method of forming, and the resulting semiconductor structure. The method may include removing a portion of an Mx+1 layer insulator above an Mx conductive layer located in an Mx layer insulator. The method may include depositing an Mx+1 conductive layer in the removed portion of the Mx+1 layer insulator. The method may include removing a portion of Mx+1 conductive layer to form a first portion of Mx+1 conductive layer. The method may include forming spacers above the first portion of Mx+1 conductive layer and in the removed portion of the Mx+1 layer insulator. The method may include forming a second Mx+1 conductive layer. The method may include forming a phase change material on the second Mx+1 conductive layer.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: October 27, 2020
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • DUAL HARD MASK REPLACEMENT GATE
    Publication number: 20200335336
    Abstract: A method of fabricating a semiconductor device includes depositing a first hard mask layer on a recessed gate stack arranged between gate spacers. The method further includes depositing a second hard mask layer on the first hard mask layer between the gate spacers.
    Type: Application
    Filed: April 16, 2019
    Publication date: October 22, 2020
    Inventor: EFFENDI LEOBANDUNG
  • PHASE CHANGE MEMORY
    Publication number: 20200328347
    Abstract: An embodiment of the invention may include a method of forming, and the resulting semiconductor structure. The method may include removing a portion of an Mx+1 layer insulator above an Mx conductive layer located in an Mx layer insulator. The method may include depositing an Mx+1 conductive layer in the removed portion of the Mx+1 layer insulator. The method may include removing a portion of Mx+1 conductive layer to form a first portion of Mx+1 conductive layer. The method may include forming spacers above the first portion of Mx+1 conductive layer and in the removed portion of the Mx+1 layer insulator. The method may include forming a second Mx+1 conductive layer. The method may include forming a phase change material on the second Mx+1 conductive layer.
    Type: Application
    Filed: April 11, 2019
    Publication date: October 15, 2020
    Inventor: Effendi Leobandung
  • VERTICALLY ORIENTED MEMORY STRUCTURE
    Publication number: 20200328349
    Abstract: A method for fabricating a semiconductor device including a vertically oriented memory structure includes forming at least one pillar including phase-change memory (PCM) material on at least one electrode, forming a plurality of spacers on the electrode and along sidewalls of the pillar, and forming, by processing the plurality of spacers and the pillar, a modified pillar having a vertically oriented dumbbell shape associated with a vertically oriented PCM memory structure.
    Type: Application
    Filed: April 11, 2019
    Publication date: October 15, 2020
    Inventor: Effendi Leobandung
  • Well and punch through stopper formation using conformal doping
    Patent number: 10804107
    Abstract: A method for doping fins includes, for a first dopant layer formed in a first region and a second region to a height continuously below a top portion of a plurality of fins such that an entirety of the first dopant layer is formed below the top portion of the plurality of fins, and a dielectric layer formed over the top portion of the plurality of fins, removing the dielectric layer and the first dopant layer in the first region to expose a first fin in the first region, forming a second dopant layer over the first fin, and annealing to drive dopants into the fins from the first dopant layer in the second region and from the second dopant layer in the first region.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: October 13, 2020
    Assignee: ELPIS TECHNOLOGIES INC.
    Inventors: Effendi Leobandung, Tenko Yamashita
  • Elemental mercury-containing probe card
    Patent number: 10802071
    Abstract: A probe card apparatus for wafer testing of a wafer under test, and a method of using the probe card for wafer testing. The probe card includes a printed circuit board having wafer testing circuitry. The probe card also includes a probe array including a slab having a plurality of probes, wherein each probe includes a volume of electrically-conductive fluid contained within a corresponding perforation of the slab that extends between a first surface and a second surface of the slab, wherein a first surface of each volume of electrically-conductive fluid substantially coincides with the first surface of the slab.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: October 13, 2020
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • NON-VOLATILE RESISTIVE PROCESSING UNIT
    Publication number: 20200320376
    Abstract: Semiconductor devices and methods of forming the same include forming a drain/gate contact, in an opening of a layer of dielectric material, that includes a portion that extends up along sidewalls of the opening. A drain layer is formed on a bottom surface of the drain/gate contact. A trapped insulator layer is formed on sidewalls of the drain/gate contact. A channel layer is formed in the opening. A source layer is formed on the channel layer.
    Type: Application
    Filed: April 8, 2019
    Publication date: October 8, 2020
    Inventor: Effendi Leobandung
  • Self-aligned hard mask for epitaxy protection
    Patent number: 10784169
    Abstract: A method includes isolating a first and at least a second region on a semiconductor substrate, and forming one or more devices on each of the first and at least second regions. Forming the one or more devices includes forming at least one gate structures in each of the first and at least second regions on a first surface of the substrate, depositing a spacer over the gate structures in each of the first and the at least second regions and over the first surface of the substrate, etching horizontal portions of the spacer in the first region, growing epitaxial portions in the first region in alignment with said at least one gate structure in the first region, oxidizing exposed surfaces of the epitaxial portions in the first region, and repeating the etching, growing and oxidizing steps for the at least second region.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: September 22, 2020
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Optoelectronics and CMOS integration on GOI substrate
    Patent number: 10784292
    Abstract: A single chip including an optoelectronic device on the semiconductor layer in a first region, the optoelectronic device comprises a bottom cladding layer, an active region, and a top cladding layer, wherein the bottom cladding layer is above and in direct contact with the semiconductor layer, the active region is above and in direct contact with the bottom cladding layer, and the top cladding layer is above and in direct contact with the active region, a silicon device on the substrate extension layer in a second region, a device insulator layer substantially covering both the optoelectronic device in the first region and the silicon device in the second region, and a waveguide embedded within the device insulator layer in direct contact with a sidewall of the active region of the optoelectronic device.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: September 22, 2020
    Assignee: International Business Machines Corporation
    Inventors: Effendi Leobandung, Ning Li, Devendra K. Sadana
  • Epitaxy lateral overgrowth for 3D NAND
    Patent number: 10777567
    Abstract: A three dimension Not AND (NAND) memory structure with a floating gate and a method for fabricating the same are provided. In an embodiment, a method for fabricating a 3D NAND structure includes forming a word line stack on a dielectric cap covering a semiconductor substrate. The method also includes forming a hole through the word line stack and the dielectric cap and forming a floating gate trap on a surface of the hole. The method also includes epitaxially growing a semiconductor such as silicon in the hole to form a device channel with substantially uniform grain. The method also includes forming a bit line over the channel.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: September 15, 2020
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Integrated circuit authentication using mask fingerprinting
    Patent number: 10769327
    Abstract: A method for fabricating a semiconductor chip includes controlling a chip testing device to measure, for each bit of a plurality of bits in the semiconductor chip, mask dimensions for a feature to determine variations of the feature within each bit. Based on the variations a probability of each bit being “0” or “1” is generated to provide predicated probabilities. Based on the predicted probabilities, each bit of the plurality of bits is grouped and a subset of bits is selected to provide a subset of predicted results. The chip testing unit is controlled to measure whether each bit of the subset of bits is in a state is “0” or “1” to provide measured results. The subset of predicted results is compared with the measured results to provide a comparison. Based on the comparison, determination is made that the semiconductor chip has been fabricated using an altered mask.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: September 8, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Effendi Leobandung
  • Growing Groups III-V lateral nanowire channels
    Patent number: 10763340
    Abstract: In one example, a method for fabricating a semiconductor device includes forming a mandrel comprising silicon. Sidewalls of the silicon are orientated normal to the <111> direction of the silicon. A nanowire is grown directly on at least one of the sidewalls of the silicon and is formed from a material selected from Groups III-V. Only one end of the nanowire directly contacts the silicon.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: September 1, 2020
    Assignee: International Business Machines Corporation
    Inventors: Sanghoon Lee, Effendi Leobandung, Renee Mo, Brent A. Wacaser
  • MULTI-KERNEL CONFIGURATION FOR CONVOLUTIONAL NEURAL NETWORKS
    Publication number: 20200265298
    Abstract: Methods and systems of implementing a convolutional neural network are described. In an example, a structure may receive input signals and distribute the input signals to a plurality of unit cells. The structure may include a plurality of multi-kernel modules that may include a respective set of unit cells. A unit cell may correspond to an element of a kernel being implemented in the convolutional neural network and may include a storage component configured to store a weight of a corresponding element of the kernel. A first pass gate of the unit cell may be activated to pass a stored weight of the unit cell to a plurality of operation circuits in the corresponding unit cell, such that the stored weight may be applied to the input signals. The structure may generate a set of outputs based on the application of the stored weights to the input signals.
    Type: Application
    Filed: February 19, 2019
    Publication date: August 20, 2020
    Inventors: Effendi Leobandung, Malte Rasch, Xiao Sun, Yulong Li, Zhibin Ren
  • RESISTIVE PROCESSING UNITS WITH COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR NON-VOLATILE ANALOG MEMORY
    Publication number: 20200258942
    Abstract: A cross-bar array includes one or more input row lines, one or more output column lines, one or more resistive processing units (RPUs) coupled at one or more intersections of the input row lines and the output column lines, and a control circuit. A given one of the RPUs includes an analog memory element including a first terminal coupled to a given one of the input row lines and a second terminal coupled to a given one of the output column lines. The analog memory element includes a complementary metal-oxide-semiconductor structure including an n-type field-effect transistor and a p-type field-effect transistor. A gate of the n-type field-effect transistor is coupled to a gate of the p-type field effect transistor to provide a floating gate. The control circuit is configured to read a synaptic weight value of the given RPU by measuring a stored electrical charge of the floating gate.
    Type: Application
    Filed: February 11, 2019
    Publication date: August 13, 2020
    Inventor: Effendi Leobandung
  • High resistance readout FET for cognitive device
    Patent number: 10741560
    Abstract: A semiconductor device includes a source region and a drain region formed in a transistor structure. A channel region is disposed between the source region and the drain region. A cladding layer is formed on the channel region, the cladding layer including a semiconductor material. A gate dielectric of a gate structure is formed on the cladding layer.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: August 11, 2020
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Multi-chip modules
    Patent number: 10741532
    Abstract: A multi-chip module includes a first semiconductor component including a first set of connections having a first pitch dimension and at least a second set of connections having a second pitch dimension, wherein the first pitch dimension is smaller than the second pitch dimension. The multi-chip module further includes a second semiconductor component interconnected with the first set of connections of the first semiconductor component. The multi-chip module further includes at least a third semiconductor component interconnected with the second set of connections of the first semiconductor component and wherein a surface of the third semiconductor component is adhered to a surface of the second semiconductor component, wherein the surfaces at least partially overlap one another.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: August 11, 2020
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Resistive processing units with complementary metal-oxide-semiconductor non-volatile analog memory
    Patent number: 10741611
    Abstract: A cross-bar array includes one or more input row lines, one or more output column lines, one or more resistive processing units (RPUs) coupled at one or more intersections of the input row lines and the output column lines, and a control circuit. A given one of the RPUs includes an analog memory element including a first terminal coupled to a given one of the input row lines and a second terminal coupled to a given one of the output column lines. The analog memory element includes a complementary metal-oxide-semiconductor structure including an n-type field-effect transistor and a p-type field-effect transistor. A gate of the n-type field-effect transistor is coupled to a gate of the p-type field effect transistor to provide a floating gate. The control circuit is configured to read a synaptic weight value of the given RPU by measuring a stored electrical charge of the floating gate.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: August 11, 2020
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • SIDEWALL IMAGE TRANSFER NANOSHEET
    Publication number: 20200251556
    Abstract: A method for forming active regions of a semiconductor device comprising forming a nanosheet stack on a substrate, forming the nanosheet stack comprising forming a sacrificial nanosheet layer on the substrate, and forming a nanosheet layer on the sacrificial nanosheet layer, forming an etch stop layer on the nanosheet stack, forming a mandrel layer on the etch stop layer, removing portions of the mandrel layer to form a mandrel on the etch stop layer, forming sidewalls adjacent to sidewalls of the mandrel, depositing a fill layer on exposed portions of the etch stop layer, removing the sidewalls and removing exposed portions of the etch stop layer and the nanosheet stack to expose portions of the substrate.
    Type: Application
    Filed: April 20, 2020
    Publication date: August 6, 2020
    Inventors: Effendi Leobandung, Tenko Yamashita
  • COMPACT RESISTIVE RANDOM ACCESS MEMORY INTEGRATED WITH A PASS GATE TRANSISTOR
    Publication number: 20200235295
    Abstract: A method of forming a resistive random access memory (ReRAM) device is provided. The method includes depositing a lower cap layer on a substrate, depositing a dielectric memory layer on the lower cap layer, and depositing an upper cap layer on the dielectric memory layer. The method further includes removing portions of the lower cap layer to form a lower cap slab, dielectric memory layer to form a dielectric memory slab on the lower cap slab, and upper cap layer to form an upper cap slab on the dielectric memory slab, wherein the lower cap slab, dielectric memory slab, and upper cap slab form a resistive memory element.
    Type: Application
    Filed: April 8, 2020
    Publication date: July 23, 2020
    Inventor: Effendi Leobandung