Abstract: A screen communication method and system for communicating screen data between a plurality of interconnected terminal units each having a display part and an input part, wherein each time screen modifying data is input from the display part, each of the terminal units transmits a modifying right request to another terminal unit before transmitting the screen modifying data, and obtains a modifying right under such a condition that each terminal unit receives no screen modifying request from another terminal unit within a predetermined period of time after the transmission of the first modifying right request.

Abstract: A wireless communication system includes a plurality of wireless terminals and a base station for periodically generating a fixed-length communication frame composed of an information field which includes a plurality of information slots, and first and second control fields which are arranged preceding the information field and each of which includes a plurality of time slots. Each time slot of the first control field of each communication frame is used for allowing the base station to send control data for designating a terminal which is to make the transmission or reception of data in one information slot of the information field, and each time slot of the second control field thereof is used for allowing one wireless terminal to send control data indicating a requirement for assignment of an information slot for data transmission.

Abstract: In a communication system having a base station for controlling a transmission right and a plurality of substations, a substation having data to be transmitted transmits the number of necessary fragments and its address to a request field of a communication frame. The base station uses a plurality pair of fragment slots and reply slots following the request field in the communication frame to transmit an address of a substation permitted to transmit data, to each fragment slot. The substation permitted to transmit data transmits the address of a destination substation and the data to a predetermined field following the address in one fragment slot. The destination station transmits a reply signal indicating the reception state of the data to the reply slot paired with the fragment slot.

Abstract: A switching system for integratedly switching voice, data, image information and the like. The switching system comprises a plurality of front-end modules each adapted to perform a switching processing in association with a subscriber line or a trunk line, and a single or a plurality of central modules for interconnecting the plurality of front-end modules in star-type fashion and switching information prevailing between the front-end modules, in unit of block accommodating the information and a header added thereto to contain connection control information and in accordance with the contents of the header. The front-end modules are connected to the central module via inter-module highways each having frames occurring at a predetermined period and time slots contained in each frame to carry blocks.

Abstract: A transmission system which includes a plurality of reproduction nodes connected to each other in a cascade connection via a communication line. Each node includes a timing extraction circuit for extracting a timing signal from a signal received via the communication line, a discriminating circuit for converting the received signal into a digital signal according to the timing signal, and a processing circuit for processing, based on the timing signal, the digital signal outputted from the discriminating circuit and outputting the processed digital signal to the communication line. The timing extraction circuit includes a signal delay unit for supplying the timing signal with a signal delay time greater than a delay time occurring in the processing circuit.

Abstract: A high-speed ring LAN capable of accommodating at least one public network having a signal transmission rate of 155.57 MHz, and at least one sub-LAN having a signal transmission rate of 100 MHz. The high-speed LAN has a signal transmission rate of 155.52 Mbps .times.n (n is an even number). SONET (Synchronous Optical NETwork) subframes each comprising a 9 bytes .times.9 section overhead area and a 261 bytes .times.9 virtual container 4 (VC-4) area flow in a time-divisional n-multiplexed format. The respective node devices inserted in the transmission path have one or more ports to accommodate sub-LANs or public networks. Information is exchanged in units of a fixed-length packet between a received SONET subframe and an asynchronous port whereas information is exchanged in units of a byte between the SONET subframe and a synchronous port.

Abstract: In a local area network composed of transmission lines for interconnecting a plurality of subordinate networks including synchronous apparatuses and a plurality of nodes which connect the subordinate networks to the transmission lines, information is transferred using a fixed length frame, a clock source which generates an independent clock signal and a circuit which generates a fixed length frame with the oscillation frequency of the clock source as a reference are provided in each node so as to adopt an independent clocking system, and distribution of a common synchronizing clock required for synchronous apparatuses is made by transmission while embedding transition point information of a synchronizing clock in a specific space in the fixed length frame.

Abstract: A cell signal processing circuit is provided which is capable of precisely extracting a timing signal and a cell synchronizing signal. The cell signal processing circuit is principally composed of a signal adder circuit for adding a dummy signal comprising bit signals in a direct current balanced state to an end portion of respective inputted time series cell signals, and a separator circuit for separating and outputting the time series cell signals. Each dummy signal being composed of the same number of bits "0" and "1" is added to input signals in the form of time series cells such that signal cells are exchanged at a time of a bit "0" in the dummy signal.

Abstract: A switching system exchanges communication information as fixed length cells between a plurality of incoming and outgoing highways. The fixed length cells each have a plurality of data portions with one data portion designated as a header portion for containing switching information. An address generating circuit generates read addresses and write addresses in response to the header portion of each cell and a control circuit. The plurality of cells from the incoming highways are simultaneously rotated in a rotation matrix with each of the cell's data portions rotated to a unique internal path. The data portions are then transmitted to identical write addresses in a plurality of memories via delay circuitry. The write addresses are transmitted through shift registers to the plurality of memories to allow the data portions of a single cell to occupy identical addresses within a plurality of memories.

Abstract: In a network having a plurality of node apparatus connected to a transmission line, each node apparatus segmenting a transmission message into information blocks of a predetermined length and transmitting them to the transmission line in the form of a fixed length packet (cell) having a source address, each node apparatus sequentially stores packets having different source addresses in vacant memory blocks of a buffer memory. There is written in each memory block the packet data as well as a next address pointer indicating a memory block in which the next received packet having the same source address is stored. When a packet containing the last information block of a message is received, stored in a read address queue is the address indicating the memory block which stores the first information block of the same packet.

Abstract: A high-speed ring LAN capable of accommodating at least one public network having a signal transmission rate of 155.57 MHz, and at least one sub-LAN having a signal transmission rate of 100 MHz. The high-speed LAN has a signal transmission rate of 155.52 Mbps.times.n (n is an even number). SONET (Synchronous Optical NETwork) subframes each comprising a 9 bytes.times.9 section overhead area and a 261 bytes.times.9 virtual container 4 (VC-4) area flow in a time-divisional n-multiplexed format. The respective node devices inserted in the transmission path have one or more ports to accommodate sub-LANs or public networks. Information is exchanged in units of a fixed-length packet between a received SONET subframe and an asynchronous packet whereas information is exchanged in units of a byte between the SONET subframe and a synchronous port.

Abstract: The packet switching apparatus comprises input buffers for respective input ports; a space division optical switch for transferring packets from the input buffers to a desired output port; and a controller for controlling the switching on the basis of the header information of the packets. The controller analyzes the header of the packets from each input port to determine outputtable packets so that these outputtable packets are outputted all at once after the connection of the switch has been controlled. By repeating this process, the packets are continuously switched.

Abstract: A switching system for integratedly switching voice, data, image information and the like. The switching system comprises a plurality of front-end modules each adapted to perform a switching processing in association with a subscriber line or a trunkline, and a single or a plurality of central modules for interconnecting the plurality of front-end modules in star-type fashion and switching information prevailing between the front-end modules, in unit of block accommodating the information and a header added thereto to contain connection control information and in accordance with the contents of the header. The front-end modules are connected to the central module via inter-module highways each having frames occurring at a predetermined period and time slots contained in each frame to carry blocks.

Abstract: A method and a system for bidirectional transmission/reception of data between two terminal stations, in which each transmission period is divided into a plurality of first time sections for relatively low speed data transmission and at least one second time section for relatively high speed data transmission, the direction of transmission between the terminal stations being predetermined in each of the first time sections, while the direction of transmission between the terminal stations is reversible in each of the second time sections, each second time section being preceded by one of the first time sections. Transmission of information data and control data is performed from one to the other terminal station in a predetermined direction in each first time section, and the direction of data transmission between the terminal stations in the next second time section is determined on the basis of control data contained in the relatively low speed data transmission.

Abstract: A CODEC including a coder and decoder to construct the subscriber's circuit of a digital telephone switching system or the like, wherein an analogue balancing circuit is provided between the output terminal of a post-filter and the input terminal of a pre-filter in order to effectively eliminate a return signal in the case of two-wire/four-wire conversion, and return signals not eliminated by the analogue balancing circuit are further eliminated by a digital balancing circuit.Especially in the present invention, the analogue balancing circuit is so constructed that its characteristics are independent of frequencies, and hence, the analogue balancing circuit and the digital balancing circuit are readily implemented as an LSI.

Abstract: To reduce the power dissipation of a static random access memory, a write enable signal is applied to the gates of load MOS transistors on bit lines which are connected to a memory cell. During the write-in time, the load MOS transistors are turned off so as to prevent as electric current from flowing from a power source into the earth through the memory cell.

Abstract: This invention relates to a time division switching system for exchanging audio signals, data and so on in a time division manner. This time division switchboard comprises a plurality of separate local exchange units capable of interfacing with various different circuits such as subscriber lines, trunk lines, service circuits and so on, one or a plurality of junctor high ways connected to a time switch of each of the local exchange units, and one or a plurality of tandem exchange units each having a time switch connected to the other ends of the junctor high ways and switching by the time switch. Each of the local exchange units selects a channel on an arbitrary junctor high way and transmits control information concerning other one of the local exchange units to which a calling is to be sent, to one of the tandem exchange units which has the selected junctor high way connected thereto.

Abstract: In an interface circuit which couples a two-wire line of bidirectional transmission and unidirectional four-wire receiving and transmitting lines; in order to permit the interface circuit to operate in adaptation to the fluctuation of an impedance with the two-wire line side viewed from the four-wire receiving line, the four-wire receiving line is provided with a plurality of filters and a group of switches for selecting the filters, an output of the four-wire transmitting line is compared with outputs obtained by scanning the filters, and the filter providing the minimum output difference in the comparisons is selected and connected.

Abstract: For the purpose of realizing a line circuit, especially a two-wire four-wire conversion circuit of a telephone exchange in the form of LSI and providing the conversion circuit with an impedance which is suitable to a side tone characteristic of the telephone set, in a line circuit composed of a hybrid circuit wherein the four-wire input line is connected to the two-wire subscriber line via a buffer amplifier and a terminating impedance and in addition the four-wire output line is connected to the output of a subtractor which subtracts an input signal of the four-wire input line passed through a filter circuit from a signal fed from the two-wire subscriber line, the terminating impedance is formed by a resistor component and in addition a feedback circuit having such a transfer characteristic that the impedance of the line circuit seen from the two-wire subscriber line side will become a specified complex impedance is installed between a line which couples the two-wire subscriber line to the subtractor and an

Abstract: A time-division switching unit for connecting a desired channel of a desired one of a plurality of input highways to a desired channel of a desired one of a plurality of output highways is disclosed. A frame synchronization circuit of the time-division switching unit variably delays signals of the input highways within one channel period, writes the signals to a speech memory for each channel, modifies write addresses to the speech memory to attain frame synchronization, extracts frame synchronization signals of the respective highways from the input and output of the speech memory, and controls the amount of delay within one channel period and the amount of address modification by the extracted synchronization signals.