Abstract: A method for manufacturing a field effect transistor, includes: forming a mask of an insulating film on a semiconductor layer containing Si formed on a semiconductor substrate; forming the semiconductor layer into a mesa structure by performing etching with the use of the mask, the mesa structure extending in a direction parallel to an upper face of the semiconductor substrate; narrowing a distance between two sidewalls of the mesa structure and flattening the sidewalls by performing a heat treatment in a hydrogen atmosphere, the two sidewalls extending in the direction and facing each other; forming a gate insulating film covering the mesa structure having the sidewalls flattened; forming a gate electrode covering the gate insulating film; and forming source and drain regions at portions of the mesa structure, the portions being located on two sides of the gate electrode.

Abstract: A resin kneaded material has not more than 30 pores having a pore diameter of not less than 20 ?m in a surface area of 4.00 mm2.

Abstract: An encapsulating sheet is obtained by subjecting a kneaded material to plastic working, the kneaded material including an epoxy resin represented by General Formula (1) below, a curing agent, and an inorganic filler, (where R1 to R4 are the same or different, and each represents a methyl group or a hydrogen atom; and X represents —CH2—, —O—, or —S—).

Abstract: A method for manufacturing a field effect transistor, includes: forming a mask of an insulating film on a semiconductor layer containing Si formed on a semiconductor substrate; forming the semiconductor layer into a mesa structure by performing etching with the use of the mask, the mesa structure extending in a direction parallel to an upper face of the semiconductor substrate; narrowing a distance between two sidewalls of the mesa structure and flattening the sidewalls by performing a heat treatment in a hydrogen atmosphere, the two sidewalls extending in the direction and facing each other; forming a gate insulating film covering the mesa structure having the sidewalls flattened; forming a gate electrode covering the gate insulating film; and forming source and drain regions at portions of the mesa structure, the portions being located on two sides of the gate electrode.

Abstract: Provided is a method of producing a semiconductor device having a structure wherein a semiconductor chip 3 is mounted on a wiring circuit substrate 2 and sealed with a resin. A wiring circuit substrate 2 having a connecting conductor portion that can be connected to an electrode of the chip is formed on a metal support layer 1 in a way such that the substrate can be separated from the metal support layer, the chip 3 is mounted on the wiring circuit substrate 2, a sheet-shaped resin composition T is placed on the chip and heated on the chip to seal the chip, and the metal support layer is separated and divided to obtain individual semiconductor devices.

Abstract: An epoxy resin composition for semiconductor encapsulation, which comprises: (A) an epoxy resin having at least two epoxy groups in a molecule thereof; (B) a compound having at least two phenolic hydroxyl groups in a molecule thereof; and (C) particles of a compound represented by general formula (1), the particles having a maximum particle diameter of not greater than 30 ?m and a standard deviation of not greater than 5 ?m, the particles being dispersed in the epoxy resin composition: wherein X1 to X5, which may be the same or different, are each a hydrogen atom, an alkyl group having 1 to 9 carbon atoms, or a fluorine atom. The epoxy resin composition is an encapsulation material excellent in pot life, fluidity and curability, and has a lower chloride ion content. The epoxy resin composition provides a highly reliable semiconductor device excellent in moisture resistant reliability.

Abstract: In a method of heat treating a wafer obtained by slicing a silicon single crystal ingot manufactured by the Czochralski method, a rapid heating/cooling heat treatment is carried out by setting a holding time at an ultimate temperature of 1200° C. or more and a melting point of silicon or less to be equal to or longer than one second and to be equal to or shorter than 60 seconds in a mixed gas atmosphere containing oxygen having an oxygen partial pressure of 1.0% or more and 20% or less and argon, and an oxide film having a thickness of 9.1 nm or less or 24.3 nm or more is thus formed on a surface of the silicon wafer.

Abstract: The invention is to provide a method for heat treating a silicon wafer reducing grown-in defects while suppressing generation of slip during RTP and improving surface roughness of the wafer. The method performing a first heat treatment while introducing a rare gas, the first heat treatment comprising the steps of rapidly heating the wafer to T1 of 1300° C. or higher and the melting point of silicon or lower, keeping the wafer at T1, rapidly cooling the wafer to T2 of 400-800° C. and keeping the wafer at T2; and performing a second heat treatment while introducing an oxygen gas in an amount of 20-100 vol. %, the second heat treatment comprising the steps of keeping the wafer at T2, rapidly heating the wafer from T2 to T3 of 1250° C. or higher and the melting point of silicon or lower, keeping the wafer at T3 and rapidly cooling the wafer.

Abstract: A thermosetting encapsulation adhesive sheet which is used for encapsulating a chip type device (1) having connection electrodes (bumps) (3) and mounted on a wiring circuit board (2). The thermosetting encapsulation adhesive sheet is composed of an epoxy resin composition having a viscosity of 5×104 to 5×106 Pa·s as measured at a temperature of 80 to 120° C. before thermosetting thereof. The thermosetting encapsulation adhesive sheet makes it possible to conveniently encapsulate a hollow device with an improved yield.

Abstract: A silicon wafer for preventing a void defect in a bulk region from becoming source of contamination and slip generation in a device process is provided. And a heat-treating method thereof for reducing crystal defects such as COP in a region near the wafer surface to be a device active region is provided. The silicon wafer has a surface region 1 which is a defect-free region and a bulk region 2 including void defect of a polyhedron whose basic shape is an octahedron in which a corner portion of the polyhedron is in the curved shape and an inner-wall oxide film the void defect is removed. The silicon wafer is provided by performing a heat-treating method in which gas to be supplied, inner pressure of spaces and a maximum achievable temperature are set to a predetermined value when subjecting the silicon wafer produced by a CZ method to RTP.

Abstract: The present invention relates to a method for manufacturing an electronic parts device allowing for easy overmolding and underfilling without requiring a jig for preventing leakage of the melted resin composition, and a resin composition sheet for electronic parts encapsulation used therein.

Abstract: A label sheet for cleaning is formed of a label for cleaning including a cleaning layer having a 180° peeling adhesion to a silicon wafer of 0.20 N/10 mm or less after receiving an active energy and an adhesive layer provided on one of surfaces of said cleaning layer, and a separator on which the label is removably provided through the adhesive layer.

Abstract: A label sheet for cleaning is formed of a label for cleaning including a cleaning layer having a 180° peeling adhesion to a silicon wafer of 0.20 N/10 mm or less after receiving an active energy and an adhesive layer provided on one of surfaces of said cleaning layer, and a separator on which the label is removably provided through the adhesive layer.

Abstract: In a manufacturing method for a silicon wafer, a first heat treatment process is performed on the silicon wafer while introducing a first gas having an oxygen gas in an amount of 0.01 vol. % or more and 1.00 vol. % or less and a rare gas, and a second heat treatment process is performed while stopping introducing the first gas and introducing a second gas having an oxygen gas in an amount of 20 vol. % or more and 100 vol. % or less and a rare gas. In the first heat treatment process, the silicon wafer is rapidly heated to first temperature of 1300° C. or higher and a melting point of silicon or lower at a first heating rate, and kept at the first temperature. In the second heat treatment process, the silicon wafer is kept at the first temperature, and rapidly cooled from the first temperature at a first cooling rate.

Abstract: A method for manufacturing a field effect transistor, includes: forming a mask of an insulating film on a semiconductor layer containing Si formed on a semiconductor substrate; forming the semiconductor layer into a mesa structure by performing etching with the use of the mask, the mesa structure extending in a direction parallel to an upper face of the semiconductor substrate; narrowing a distance between two sidewalls of the mesa structure and flattening the sidewalls by performing a heat treatment in a hydrogen atmosphere, the two sidewalls extending in the direction and facing each other; forming a gate insulating film covering the mesa structure having the sidewalls flattened; forming a gate electrode covering the gate insulating film; and forming source and drain regions at portions of the mesa structure, the portions being located on two sides of the gate electrode.

Abstract: A method for manufacturing a field effect transistor, includes: forming a mask of an insulating film on a semiconductor layer containing Si formed on a semiconductor substrate; forming the semiconductor layer into a mesa structure by performing etching with the use of the mask, the mesa structure extending in a direction parallel to an upper face of the semiconductor substrate; narrowing a distance between two sidewalls of the mesa structure and flattening the sidewalls by performing a heat treatment in a hydrogen atmosphere, the two sidewalls extending in the direction and facing each other; forming a gate insulating film covering the mesa structure having the sidewalls flattened; forming a gate electrode covering the gate insulating film; and forming source and drain regions at portions of the mesa structure, the portions being located on two sides of the gate electrode.

Abstract: Provided is a method of producing a semiconductor device having a structure wherein a semiconductor chip 3 is mounted on a wiring circuit substrate 2 and sealed with a resin. A wiring circuit substrate 2 having a connecting conductor portion that can be connected to an electrode of the chip is formed on a metal support layer 1 in a way such that the substrate can be separated from the metal support layer, the chip 3 is mounted on the wiring circuit substrate 2, a sheet-shaped resin composition T is placed on the chip and heated on the chip to seal the chip, and the metal support layer is separated and divided to obtain individual semiconductor devices.

Abstract: A method for manufacturing a field effect transistor, includes: forming a mask of an insulating film on a semiconductor layer containing Si formed on a semiconductor substrate; forming the semiconductor layer into a mesa structure by performing etching with the use of the mask, the mesa structure extending in a direction parallel to an upper face of the semiconductor substrate; narrowing a distance between two sidewalls of the mesa structure and flattening the sidewalls by performing a heat treatment in a hydrogen atmosphere, the two sidewalls extending in the direction and facing each other; forming a gate insulating film covering the mesa structure having the sidewalls flattened; forming a gate electrode covering the gate insulating film; and forming source and drain regions at portions of the mesa structure, the portions being located on two sides of the gate electrode.

Abstract: A cleaning sheet for cleaning foreign matters away from the interior of the substrate processing equipment is provided. The cleaning sheet includes a cleaning layer having substantially no tackiness and having a tensile modulus of not lower than 0.98 N/mm2 as determined according to JIS K7127. Alternatively, the cleaning sheet includes a cleaning layer having a Vickers hardness of not lower than 10 MPa.

Abstract: A cleaning sheet comprises a cleaning layer provided on one side of a base material, from which cleaning layer F?, Cl?, Br?, NO2?, NO3?, PO43?, SO42?, Na+, NH4+ and K+ are extractable with pure water each in an amount of not greater than 20 ppm, when extracted under boiling at 120° C. for 1 hour, and a pressure-sensitive adhesive layer provided on the other side of the base material, a carrying material with cleaning capacity comprising the aforementioned cleaning sheet laminated on a carrying material with a pressure-sensitive adhesive layer. The present disclosure also relates to a method for cleaning a substrate processing equipment which comprises conveying the aforementioned carrying material with cleaning capacity into the substrate processing equipment.