Abstract: A digital transmission system is disclosed having a transmitter and a receiver for transmitting and receiving a digital audio signal. The digital audio signal is in the form of samples of a specific wordlength and occurring at a specific sampling rate. The transmitter including an input terminal for receiving the digital audio signal and for receiving a first information word having a relationship with the specific wordlength and a second information word having a relationship with the specific sampling rate. A formatting unit is present far combining the digital audio signal and the first and second information words into a serial datastream suitable for transmission via a transmission medium. The wordlength of the samples in the digital audio signal, expressed in number of bits, being equal to n, where n is an integer larger than zero, and the sampling rate is equal to 2p.

Abstract: A signal converter includes a digital/analog converter and a low pass filter. The converter includes control means for amending the ratio of sampling frequencies of the D/A input signal and the D/A output signal or of the low pass filter.

Abstract: A receiver with an integrated mixer/Sigma-Delta Modulator configuration for digitizing a relatively low-bandwidth signal modulated on a high-frequency carrier, for example in a radio receiver. The Sigma-Delta Modulator has an continuous-time loop filter (F1, F2) with anti-aliasing characteristics which eliminate the need for a separate lowpass filter between the mixer (MX) and the Sigma-Delta Modulator.

Abstract: A device has a first operational state for writing information onto a record carrier and a second operational state for reading information from a record carrier. The device includes a phase-locked loop for generating a clock signal from a reference signal and a control unit for generating a pulsed transducer control signal in response to an information signal and the clock signal. The device also includes a generating transducer for generating physically detectable patterns in the record carrier in response to the transducer control signal and a read transducer for generating a read signal in response to physically detectable patterns in the record carrier in the second operational state that includes a radiation source. The device further includes a power supply which supplies the radiation source with an electric power. The phase-locked loop includes a memory for memorizing, in the first operational state, a memory value which is a measure of the supplied clock signal.

Abstract: Sigma-delta modulator in which the gain stage (20) of the input network and the gain stage (22) of the feedback network are regularly interchanged (“chopped”). This averages out the difference between the two gain stages, thus defining the gain of the system accurately. The difference in gain between the two gain stages is modulated on the chopping frequency, which may be outside the frequency band of interest. Furthermore, by using fully differential circuitry the chopping can be effected in such a manner that the offset and flicker noise of the two gain stages are modulated to the chopping frequency.

Abstract: Sigma-delta analog-to-digital converter topology with an error signal branch including a subtractor (10), a loop filter (4), and a quantizer (6), and a feedback branch including a digital-to-analog converter (8). The gain error caused by a return-to-zero switch in the feedback branch is cancelled by moving the return-to-zero switch (20) to the signal error branch.

Abstract: The device for amplifying input signals (10) comprises a control stage (12) and a switching bridge amplifier (14), which is coupled to said control stage via at least first and second control signals (16, 18). The bridge amplifier (14) can be switched in at least two states, in dependence upon the control signals (16, 18). The control stage (12) is embodied so as to control only a single substantially passive state of the bridge amplifier (14), as a result of which relatively small switching losses occur.

Abstract: A PWM amplifier comprising a comparator and an integrator is known to amplify, for example, audio signals. One drawback of the known PWM amplifiers is the maximally achievable loop gain is low. To overcome the disadvantages of the prior art PWM amplifiers, a PWM amplifier is provided with a second integrator in the feedback loop.

Abstract: A digital transmission system having a transmitter and a receiver for transmitting and receiving a digital audio signal. The digital audio signal is in the form of samples of a specific wordlength and occurring at a specific sampling rate. The transmitter includes an input terminal for receiving the digital audio signal and for receiving a first information word having a relationship with the specific wordlength and a second information word having a relationship with the specific sampling rate. The transmitter also includes a formatting unit for combining the digital audio signal and the first and second information words into a serial datastream suitable for transmission via a transmission medium. The wordlength of the samples in the digital audio signal, expressed in number of bits, is equal to n, where n is an integer larger than zero, and the sampling rate is equal to 2p.

Abstract: A digital transmission system is disclosed having a transmitter (11) and a receiver (12) for transmitting and receiving a digital audio signal. The digital audio signal is in the form of samples of a specific wordlength (WL) and occurring at a specific sampling rate.

Abstract: An amplifier arrangement having a first and a second output transistor, which are drain-connected to the output terminal. A driver stage (100), prevents the output transistors from becoming non-conductive, thereby reducing cross-over distortion. This is achieved by applying an input signal via the sources of a source coupled transistor pair to the gates of the output transistors. Additional source followers are provided for defining gate-sources voltages which prevent the output transistors from becoming non-conductive.

Abstract: A voltage converter provided with charge pumps in which conventional rectifier diodes are replaced by output transistors. The output transistors at the same time act as voltage stabilizers. This also renders the ripple value of the voltage at the output terminal low when no smoothing capacitor, or a smoothing capacitor with a comparatively low capacitance value, is coupled to the output terminal.

Abstract: An oscillator in which the transconductance of an amplification transistor (T0) is limited through a measurement of the potential at the input electrode (G0) of the amplification transistor (T0) by means of a differential pair (T1, T2) for safeguarding the starting of the oscillator.

Abstract: An oscillator provided with an amplitude controller (AMPREG1) which is coupled by an input (G1) to an amplitude reference terminal (AMPREF1). The amplitude of the oscillator signal at the output terminal (KU) can be adjusted through coupling of a voltage-generating means to the amplitude reference terminal (AMPREF1).

Abstract: An integrated circuit, includes an output stage with an input which is coupled to a first and a second gate of an NMOS transistor and a PMOS transistor, respectively, and an output which is connected to a first and a second supply terminal via the PMOS transistor and the NMOS transistor, respectively. The output is coupled to the first gate via a series connection of a Miller capacitor and a switching circuit. The Miller capacitor limits the rate of increase of the voltage on the output, thus preventing interference. The switching circuit is rendered non-conductive ahead of the switching over from logic low to logic high. This prevents sudden discharging of the Miller capacitor which would otherwise cause interference itself.

Abstract: A first signal processor stage of an audio amplifier arrangement influences the signal strength of a received audio signal for at least part of the frequency range of the received audio signal. An output amplifier stage amplifies the audio signal influenced by the first signal processor stage. The audio amplifier arrangement further includes a transformer having a primary winding connectable to a mains voltage and having a secondary winding connected to an AC/DC converter whose outputs are connected to at least the output amplifier stage for feeding the output amplifier stage. A detection circuit generates a detection signal (Vms) which is related to the power load of the transformer. An analysis circuit detects in response to the detection signal whether the rise in temperature occurring in the transformer due to the power load has exceeded a specific norm.

Abstract: A sawtooth oscillator includes a current source having an output coupled to a first capacitor for supplying it with a charge current (I). A discharge circuit discharges the first capacitor during a discharge period (TDS) in response to a voltage on the first capacitor. A second capacitor is coupled to the output of the current source. A switch interrupts the supply of charge current to the first capacitor during an interrupt period (TIS). Part of the charge current occurs during the discharge period (TDS). Subsequent to the interrupt period, the first capacitor receives a charge surplus built up by the charge current in the second capacitor. The current supply to the first capacitor is temporarily interrupted at least during a part of the discharge period. The second capacitor operates as an auxiliary capacitor in which a charge is stored which would otherwise have been supplied to the first capacitor.

Abstract: A differential amplifier with common-mode rejection has input transistors (T1, T2) whose drains are coupled to a first output terminal (10) and a second output terminal (12), respectively, and to the drains of current-source transistors (T3, T4) whose sources are each connected to a supply terminal (18) via a parallel arrangement of two control transistors (T5A/T6A, T5B/T6B) in order to reject the common-mode component at the output terminals (10, 12). Of each pair of control transistors the gate of the one transistor (T5A, T5B) is coupled to the first output terminal (10) and the gate of the other transistor (T5B, T6B) is coupled to second output terminal (12).

Abstract: An amplifier arrangement which includes a first and a second output transistor each having a base, a collector and an emitter. A bias stage generates a bias voltage between the bases of the first and the second output transistor. The emitters of the first and the second output transistors are coupled to an output terminal. The bias voltage has a negative thermal response, and one element (e.g. a transistor) of the bias stage is thermally coupled to the first and the second output transistor. In order to preclude thermal instability of the amplifier arrangement, the bias stage is adapted to generate a first voltage having a first negative thermal response by means of the one element of the bias stage and to generate a second voltage opposite to the first voltage and having a second negative thermal response. The bias voltage is equal to the sum of the first and the second voltages, the first voltage being larger in absolute value than the second voltage.

Abstract: An arrangement for supplying energy to a load having a low-pass frequency characteristic. A binary signal having a low-frequency component and a strong high-frequency component having a predetermined frequency is applied to a rejection filter adjusted to suppress the predetermined frequency. The rejection filter is of a type producing a ternary output signal.The load is supplied by means of a control circuit in such a way that, in response to the signal level at the output of the rejection filter, the load is supplied with a positive polarity, with a negative polarity, or the energy supply to the load is interrupted. In this manner a ternary energy supply is obtained having low power dissipation in the control circuit and in the load.