Abstract: A sigma-delta modulator comprising a low-pass filter of the Nth order, which is constituted by a series combination of N first-order integrating sections (6.1, 6.2, 6.3, . . . , 6.N) each comprising an integrator (12.1, 12.2, 12.3, . . . , 12. N) and a limiter (14.1, 14.2, 14.3, . . . , 14.N). The individual output signals of the sections are weighted by means of corresponding weighting amplifiers (16.1, 16.2, 16.3, . . . , 16.N) and the weighted signals are added together by an adder stage (18). The gains of the sections and the limit values of the limiters are selected so that the last limiter (14.N) in the series arrangement is activated first as the input signal level to the sigma-delta modulator increases, then the last-but-one limiter, and so on. This reduces the order of the filter system each time by one section as the input signal level increases above each successive limit value, thereby causing the sigma-delta modulator to remain stable at all signal levels.

Abstract: A digital phase-locked-loop circuit is provided for deriving from a sequence of samples (J.sub.1, . . . J.sub.20) of a band-limited data signal (Vt), the phase of the data signal at the sampling instants. The circuit includes a discrete-time oscillator 10 for generating a sequence of phase values (F.sub.1, . . . F.sub.20) which characterize a periodic signal (Vk1) having an amplitude which varies as a linear function of time between two constant limit values (E.sub.1, -E). The frequency of the periodic signal (Vk1) characterized by the phase values is proportional to a control value (I). An interpolation circuit (2) derives from the samples (J.sub.1, . . . J.sub.20) the relative positions (tf/T) occupied by the detection-level crossings of the data signal (Vt) relative to the sampling instants. A phase detector (3) derives the difference (.DELTA.F) between the actual phase of the data signal (Vt) and the phase as indicated by the phase values (F) from the relative positions (tf/T) and the phase values (F).

Abstract: A digital phase-locked-loop circuit is provided for deriving from a sequence of samples (J.sub.1, . . . J.sub.20) of a band-limited data signal (Vt), the phase of the data signal at the sampling instants. The circuit includes a discrete-time oscillator 10 for generating a sequence of phase values (F.sub.2, . . . F.sub.20) which characterize a periodic signal (Vk1) having an amplitude which varies as a linear function of time between two constant limit values (E, -E). The frequency of the periodic signal (Vk1) characterized by the phase values is proportional to a control value (I). An interpolation circuit (2) derives from the samples (J.sub.1, . . . J.sub.20) the relative positions (tf/T) occupied by the detection-level crossings of the data signal (Vt) relative to the sampling instants. A phase detector (3) derives the difference (.DELTA.F) between the actual phase of the data signal (Vt) and the phase as indicated by the phase values (F) from said relative positions (tf/T) and the phase values (F).

Abstract: A current source arrangement in which the equality of a number of current sources (1-8) constituted by transistors is improved in that each of these current sources (1-8) is constituted by a number of transistors which are arranged regularly in a matrix on the surface area of an integrated circuit.

Abstract: A high accuracy current source arrangement is made up of a number of binary-weighted current sources each of which comprises a plurality of indentical transistors which are arranged regularly in a matrix of transistor elements on the surface area of an integrated circuit. The matrix of transistors is distributed over the area of the IC to provide the maximum spacing between the matrix elements (transistors) of each respective current source thereby to minimize the influence of variations in IC parameters or the like on the accuracy of the relationship of the binary-weighted currents to one another.

Abstract: A power supply circuit in which the mains voltage which is applied across the primary winding (2) of a transformer (1) to generate a first direct voltage across a first capacitor (C.sub.1) by means of a secondary winding (3) and a first rectifier (D.sub.1) and a second direct voltage is generated across a second capacitor (C.sub.2) by means of a tertiary winding (4) and a second rectifier (D.sub.2). If the mains voltage is not connected, a first direct voltage is supplied by a battery (15) connected in parallel with the first capacitor (C.sub.1). The second direct voltage then is generated from the battery voltage of the battery (15) by means of an inverter circuit (20), a transistor (T.sub.1), the secondary winding (3) and the the tertiary winding (4).

Abstract: A class-G amplifier comprises first, second and third terminals connected to a load, first supply voltage (V.sub.1) and second supply voltage (V.sub.2), respectively, where V.sub.2 >V.sub.1. First (T.sub.1) and second (T.sub.2) transistors are series-connected between the first and third terminals with the collector of T.sub.1 coupled via first diode (D.sub.1) to the second terminal. A third emitter follower transistor (T.sub.3) has a B/E junction coupled between a signal input terminal and base of T.sub.1. A first current source (5) couples the third terminal and third transistor. A driver circuit includes a first current path between the third terminal and emitter of T.sub.3 comprising, in series, a second current source (7), a fourth transistor (T.sub.5) and second diode (D.sub.4). A second current path between a junction point (3) and common point (11) comprises, in series, third (D.sub.2) and fourth (D.sub.3) diodes and a third current source (8).

Abstract: A D/A converter which converts a one-bit coded signal into an analog signal by means of an integrator comprising an operational amplifier (1) having an output (4) fed back to the inverting input (3) by means of a first capacitor (C.sub.1) and a resistor (R.sub.1). Depending on the value of the one-bit coded signal a positive current pulse or a negative current pulse is applied to the inverting input (3) of the integrator. The positive current pulses are generated by means of a switching network (10) comprising a second capacitor (C.sub.3) which is switched by means of a plurality of switches (S.sub.1 to S.sub.4). The negative current pulses are generated by means of a switching network (20) comprising a third capacitor (C.sub.4) which is switched by a plurality of further switches (S.sub.5 to S.sub.8). In order to ensure that the analog output signal is not distorted as a result of the positive and negative current pulses, a fourth capacitor (C.sub.2) is connected to the inverting input of the integrator.

Abstract: A high-efficiency class-G type amplifier comprises a first transistor (T.sub.1), having its collector connected to a first supply voltage (V.sub.1) via a first diode (D.sub.1) and a second transistor (T.sub.2), connected in series with the first transistor and which has its collector connected to a second supply voltage (V.sub.2). The series arrangement of a second (D.sub.2), a third (D.sub.3) and a fourth diode (D.sub.4) is connected between the bases of the first and the second transistor (T.sub.1, T.sub.2) the fourth diode (D.sub.4) is poled in a direction opposite to that of the second (D.sub.2) and the third diode (D.sub.3). The series arrangement of a first resistor (R.sub.1) and the emitter-collector path of a first current-source transistor (T.sub.4) connects the second supply voltage to the anode of the fourth diode (D.sub.4). The junction point (5) between the first resistor (R.sub.1) and the current-source transistor (T.sub.4) is connected to the output (2) by means of a capacitor (C.sub.1).

Abstract: A high efficiency class-G amplifier comprises first (2), second (4) and third (10) terminals connected to a load, a first (V.sub.1) and second (V.sub.2) supply voltage, respectively, where voltage V.sub.2 >V.sub.1. First (T.sub.1) and second (T.sub.2) transistors are serially connected between the first and third terminals. A third transistor (T.sub.3, emitter-follower) couples a signal input terminal (6) to the base of the first transistor. A first diode (D.sub.1) connects the collector of T.sub.1 to the second terminal. A driver circuit includes a current path between the third terminal and a common terminal (11) having, in series, a first current source (7), second (D.sub.2) and third (D.sub.3) diodes and a second current source (8). A fourth diode (D.sub.4) connects junction point 3 to junction point 9. A fifth diode (D.sub.5) connects the emitter of the third transistor to the second current source.

Abstract: A switching device is provided for suppressing a signal. A signal source is connected to a first differential amplifier. The first differential amplifier receives an operating current from a current source. A second differential amplifier receives an operating current from a current source, and has an input connected to a common signal terminal. A conversion circuit connects the first differential amplifier and second differential amplifier outputs. An output amplifier is connected to the conversion circuit output for amplifying a single ended output of the conversion circuit. A signal from the output amplifier is suppressed by switching the operating current of said first differential amplifier and said output amplifier off, while simultaneously switching the operating current of the second differential amplifier on.

Abstract: In order to avoid the occurrence of spurious signals on the output (3) of an electrical circuit (1) when the circuit power supply is switched on and off, the output (3) is disconnected from the remainder of the circuit under the control of a control device (5). The control device comprises a current mirror whose input path (T.sub.1, R.sub.1) is in series with a first resistor (R.sub.3) and whose output path (T.sub.2, R.sub.2) is in series with a capacitor (C.sub.1) between the first (10) and the second (20) power supply terminal. The input and the output path are connected to the bases (12, 14) of two transistors (T.sub.3, T.sub.4) which are connected as a differential pair and whose common emitters are coupled to the positive power supply terminal (10) by means of a second resistor (R.sub.4). After switching on of the power supply the capacitor (C.sub.1) is charged via the current mirror (T.sub.1, R.sub.1 ; T.sub.2, R.sub.2 ), so that the differential-pair transistor (T.sub.

Abstract: The invention relates to a circuit arrangement having several signal paths which can be activated by a switchable current source. For the current source, use is made of I.sup.2 L gates whose injector connections are combined in two groups. When a switch-over is made from one signal path to another, a decreasing current is applied to the injector connection of the I.sup.2 L gate connected to one signal path while an increasing current is applied to the corresponding connection of the I.sup.2 L gate associated with the other signal path.

Abstract: An amplifier arrangement includes a first section and a second section. The second section has an output transistor which is protected by a protection circuit. The protection circuit acts on the input of the second section in order to obtain a higher gain in the protection loop. In order to preclude instabilities, the protection circuit has a falling frequency response with a flat portion in view of the frequency compensation of the second section.

Abstract: A differential amplifier with single-ended drive includes a balancing impedance (20) coupled between the base of the transistor (3) connected to the signal input (1) and the common point (9) of the two emitters of the transistors (3,4), which form a differential pair. The capacitance value of the capacitor (20) is substantially equal to the capacitance value of the stray capacitance (19) of the collector-substrate junction of a transistor (10) which forms a current source. This provides a symmetry of the capacitances between the input (1) and the common point (9) and between the common point (9) and ground via the transistor (10). This results in an improved balance in the output signals at the output terminals (5,6) and a flat frequency response of the differential amplifier for higher frequencies.

Abstract: For a satisfactory cross-over behavior of the transistors T.sub.1 and T.sub.2 of push-pull amplifier comprising an input 2 and an output 3, it is necessary that the sum of the base-emitter voltages of the transistors T.sub.1 and T.sub.2 remains substantially constant. For this purpose a first voltage-current converter 5 is coupled between the base and the emitter of transistor T.sub.1, the inverting input of this converter being coupled to the base of transistor T.sub.1 via a first reference-voltage source 8 and the non-inverting input to the emitter of transistor T.sub.1. Similarly, a second voltage-current converter 9 and a second reference-voltage source 12 are arranged between the base and the emitter of transistor T.sub.2. The output currents of the first and the second voltage-current converters 5 and 9 are compared with each other in the combining circuit 14 which drives the control amplifier 15, which in its turn controls the base-emitter voltage of transistor T.sub.

Abstract: An operational amplifier with frequency compensation is described. The amplifier includes a first amplifier with a low-impedance output followed by a transconductance amplifier with a capacitive feed-forward. The transconductance amplifier is followed by a Miller integrator.

Abstract: In a digital-to-analog converter for bipolar signals all the bits change when the signals pass through the zero level. This results in a poor signal-to-noise ratio owing the small signal and the large noise contribution by the switching transients. The invention proposes to add a digital number to or subtract it from the digital input signal as an offset. As a result of this, the switching point is shifted towards a higher amplitude, which improves the signal-to-noise ratio and the distortion in the case of digital audio signals.

Abstract: The invention relates to an integrated resistor formed in an epitaxial layer and provided with at least one tap. In order to reduce field effect action between the resistor and the epitaxial layer, the voltage on the two ends of the epitaxial layer underneath the resistor tracks the voltage on the two ends of the resistor. Moreover, the epitaxial layer is short-circuited by means of buried layers at the locations where the resistance layer also exhibits a short-circuit, such as underneath the contact area of the tap.

Abstract: In a known current source arrangement which generates a current whose temperature coefficient is only equal to zero at one specific temperature, steps are taken, in accordance with the invention, to render the generated current independent of the temperature over a wide temperature range by compensation of the disturbing factor in the relationship between the generated current and the temperature.