Abstract: Disclosed are a heat dissipation computer and method. In one embodiment, a heat dissipation apparatus comprises a heat sink that is adapted to receive a processor mounted thereto, the heat sink comprising an internal chamber that is adapted to receive a fluid flow that removes heat from the heat sink. In one embodiment, a method for dissipating heat generated by a processor comprises forcing fluid through an internal chamber formed within a heat sink to which the processor is mounted, forcing the fluid from the internal chamber of the heat sink through at least one hollow prong that extends from the heat sink and that is in fluid communication with the internal chamber of the heat sink, and forcing fluid over exterior surfaces of the at least one hollow prong.

Abstract: Systems, methods, and computer programs for performing cache yield analysis of a processor design are provided. One embodiment is a system for testing cache performance of a processor design. Briefly described, one such system comprises: means for searching a file that contains test results for a lot of wafers; and means for identifying all processors on wafers in the lot in which a cache array has passed a cache test.

Abstract: Systems, methods, and computer programs for testing a processor design are provided. One embodiment is a system comprising: means for searching a file that contains test results for a lot of wafers at two or more voltage levels; and means for determining an optimal operational voltage based on which of the two or more voltage levels had the least test failures.

Abstract: Systems, methods, and computer programs for performing cache yield analysis of a processor design are provided. One embodiment is a method for testing cache performance of a processor design comprising: searching a file that contains cache test results for a lot of wafers; and determining at least one cache array location in at least one processor in the lot wafers processor for which a cache test has failed.

Abstract: Disclosed are a heat dissipation computer and method. In one embodiment, a heat dissipation apparatus comprises a heat sink that is adapted to receive a processor, the heat sink forming part of an enclosed interior passage, and at least one prong extending from the heat sink and positioned within the interior passage, wherein the enclosed interior passage is adapted to receive fluid forced through the interior passage. In one embodiment, a method for dissipating heat generated by a processor comprises forming an interior passage in part with a heat sink to which the processor is mounted, and forcing the fluid through the interior passage and over prongs contained within the interior passage and extending from the heat sink.

Abstract: Disclosed are a heat dissipation computer and method. In one embodiment, a heat dissipation apparatus comprises a heat sink that is adapted to receive a processor mounted thereto, the heat sink comprising an internal chamber that is adapted to receive a fluid flow that removes heat from the heat sink. In one embodiment, a method for dissipating heat generated by a processor comprises forcing fluid through an internal chamber formed within a heat sink to which the processor is mounted, forcing the fluid from the internal chamber of the heat sink through at least one hollow prong that extends from the heat sink and that is in fluid communication with the internal chamber of the heat sink, and forcing fluid over exterior surfaces of the at least one hollow prong.

Abstract: One embodiment of a method comprises retrieving test data corresponding to test results from a plurality of fuses, each one of the plurality of fuses residing on a different one of a plurality of semiconductor devices and each one of the plurality of fuses having a common location on the semiconductor devices, determining from the test data which of the plurality of fuses are defective fuses, and specifying on an output report the common location of the determined defective fuses when a number of the defective fuses are at least equal to a predefined portion of the plurality of fuses.

Abstract: One embodiment of a method for analysis of cache array test data comprises retrieving cache array test data corresponding to test results of at least one cache array, analyzing the cache array test data, determining a condition of the cache array based upon the cache array test data, and generating an output report indicating a location the determined cache array on a wafer.

Abstract: One embodiment of a method for analysis of cache array test data comprises retrieving test results for a current period of time for a first plurality of storage elements and for a historical period of time for a second plurality of storage elements; determining a plurality of attributes for each of the first storage elements and the second storage elements based upon the test results, the attributes comprising one of a good condition, a defective condition, a repairable condition and a repaired condition; determining a plurality of attribute statistics corresponding to the attributes of the first storage elements and the second storage elements; and generating an output report indicating at least two of the attribute statistics of the first storage elements and the second storage elements.

Abstract: Systems and methods are described for sharing signals across a common metal trace on a single metal layer of an integrated circuit. The signals are time division multiplexed across the common metal trace such that a single metal layer of an integrated circuit is used to multiplex signals to and from a poly-silicon layer, reducing utilization of upper metal layers of the integrated circuit.

Abstract: A data bus for a printed circuit board is disclosed having a plurality of lines separated by a substrate. A method is also disclosed for creating a bus with a reduced reflection of signal energy at the interface between the bus and a receiving agent connected to the bus. The lines in the bus include data lines and at least two strobe lines that are positioned adjacent each other to take advantage of the known impedance inherent to their dominant coupling. The bus includes separate data-line terminations and strobe-line terminations connected to the data lines and strobe lines, respectively. The separate terminations have values matched to impedances calculated from the separate sets of lines to more effectively reduce the reflected energy by more accurately matching the impedances on the lines.

Abstract: An embodiment of the invention provides a circuit and method for reducing power in dynamic circuits. A large single pre-charge FET is used to pre-charge the pre-charge nodes of all dynamic logic blocks contained in a plurality of dynamic logic blocks. The large single pre-charge FET replaces all smaller individual FETs that normally would be used. Because smaller FETs typically have more subthreshhold leakage than larger FETs, the overall subthreshhold leakage is reduced. The large pre-charge FET only replaces smaller pre-charge FETs that have the same pre-charge signal going to their gates.