Abstract: A method of forming graphene layers is disclosed. A method of improving graphene deposition is also disclosed. Some methods are advantageously performed at lower temperatures. Some methods advantageously provide graphene layers with lower resistance. Some methods advantageously provide graphene layers in a relatively short period of time.

Abstract: A method and apparatus for performing post-exposure bake cooling operations is described herein. The method begins by post exposure baking a substrate disposed on heated substrate support in a process chamber, the process chamber having a showerhead. The heated substrate support is moved to increase a distance between the heated substrate support and a cooled plate of the showerhead. The substrate is separated from the heated substrate support using a substrate lifting device. The substrate is moved into a close proximity to the cooled showerhead. The substrate is cooled until the substrate is less than about 70 degrees Celsius. The substrate is spaced away from the cooled showerhead using the substrate lifting device and aligning the substrate with a substrate transfer passage of the processing chamber for removal by a robot.

Abstract: Methods and apparatuses for minimizing line edge/width roughness in lines formed by photolithography are provided. In one example, a method of processing a substrate includes applying a photoresist layer comprising a photoacid generator to on a multi-layer disposed on a substrate, wherein the multi-layer comprises an underlayer formed from an organic material, inorganic material, or a mixture of organic and inorganic materials, exposing a first portion of the photoresist layer unprotected by a photomask to a radiation light in a lithographic exposure process, and applying an electric field or a magnetic field to alter movement of photoacid generated from the photoacid generator substantially in a vertical direction.

Abstract: Methods for depositing a dielectric material using RF bias pulses along with remote plasma source deposition for manufacturing semiconductor devices, particularly for filling openings with high aspect ratios in semiconductor applications are provided. For example, a method of depositing a dielectric material includes providing a gas mixture into a processing chamber having a substrate disposed therein, forming a remote plasma in a remote plasma source and delivering the remote plasma to an interior processing region defined in the processing chamber, applying a RF bias power to the processing chamber in pulsed mode, and forming a dielectric material in an opening defined in a material layer disposed on the substrate in the presence of the gas mixture and the remote plasma.

Abstract: Methods of reducing wafer bowing in 3D DRAM devices are described using a 3-color process. A plurality of film stacks are formed on a substrate surface, each of the film stacks comprises two doped SiGe layers having different dopant amounts and/or Si:Ge ratios and a doped silicon layer. 3D DRAM devices are also described.

Abstract: A high-pressure processing system for processing a layer on a substrate includes a first chamber, a support to hold the substrate in the first chamber, a second chamber adjacent the first chamber, a foreline to remove gas from the second chamber, a vacuum processing system configured to lower a pressure within the second chamber to near vacuum, a valve assembly between the first chamber and the second chamber to isolate the pressure within the first chamber from the pressure within the second chamber, a gas delivery system configured to increase the pressure within the first chamber to at least 10 atmospheres while the first chamber is isolated from the second chamber, an exhaust system comprising an exhaust line to remove gas from the first chamber, and a common housing surrounding both the first gas delivery module and the second gas delivery module.

Abstract: Exemplary processing methods may include forming a plasma of a silicon-containing precursor. The methods may include depositing a flowable film on a semiconductor substrate with plasma effluents of the silicon-containing precursor. The processing region may be at least partially defined between a faceplate and a substrate support on which the semiconductor substrate is seated. A bias power may be applied to the substrate support from a bias power source. The methods may include forming a plasma of a hydrogen-containing precursor within the processing region of the semiconductor processing chamber. The methods may include etching the flowable film from a sidewall of the feature within the semiconductor substrate with plasma effluents of the hydrogen-containing precursor. The methods may include densifying remaining flowable film within the feature defined within the semiconductor substrate with plasma effluents of the hydrogen-containing precursor.

Abstract: Methods for plasma enhanced chemical vapor deposition (PECVD) of silicon carbonitride films are described. A flowable silicon carbonitride film is formed on a substrate surface by exposing the substrate surface to a precursor and a reactant, the precursor having a structure of general formula (I) or general formula (II) wherein R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, and R12 are independently selected from hydrogen (H), substituted or unsubstituted alkyl, substituted or unsubstituted alkoxy, substituted or unsubstituted vinyl, silane, substituted or unsubstituted amine, or halide; purging the processing chamber of the silicon precursor, and then exposing the substrate to an ammonia plasma.

Abstract: Methods for plasma enhanced chemical vapor deposition (PECVD) of silicon carbonitride films are described. A flowable silicon carbonitride film is formed on a substrate surface by exposing the substrate surface to a precursor and a reactant, the precursor having a structure of general formula (I) or general formula (II) wherein R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, and R12 are independently selected from hydrogen (H), substituted or unsubstituted alkyl, substituted or unsubstituted alkoxy, substituted or unsubstituted vinyl, silane, substituted or unsubstituted amine, or halide; purging the processing chamber of the silicon precursor, and then exposing the substrate to an ammonia plasma.

Abstract: A method for enhancing the depth of focus process window during a lithography process includes applying a photoresist layer comprising a photoacid generator on a material layer disposed on a substrate, exposing a first portion of the photoresist layer unprotected by a photomask to light radiation in a lithographic exposure process, providing a thermal energy to the photoresist layer in a post-exposure baking process, applying an electric field or a magnetic field while performing the post-exposure baking process, and dynamically changing a frequency of the electric field as generated while providing the thermal energy to the photoresist layer.

Abstract: A high-pressure processing system for processing a layer on a substrate includes a first chamber, a support to hold the substrate in the first chamber, a second chamber adjacent the first chamber, a foreline to remove gas from the second chamber, a vacuum processing system configured to lower a pressure within the second chamber to near vacuum, a valve assembly between the first chamber and the second chamber to isolate the pressure within the first chamber from the pressure within the second chamber, a gas delivery system configured to increase the pressure within the first chamber to at least 10 atmospheres while the first chamber is isolated from the second chamber, an exhaust system comprising an exhaust line to remove gas from the first chamber, and a common housing surrounding both the first gas delivery module and the second gas delivery module.

Abstract: A method for processing a substrate is described. The method includes forming a metal containing resist layer onto a substrate, patterning the metal containing resist layer, and performing a post exposure bake on the metal containing resist layer. The post exposure bake on the metal containing resist layer is a field guided post exposure bake operation and includes the use of an electric field to guide the ions or charged species within the metal containing resist layer. The field guided post exposure bake operation may be paired with a post development field guided bake operation.

Abstract: A method and apparatus for performing post-exposure bake operations is described herein. The apparatus includes a plate stack and enables formation of a first high ion density plasma before the ion concentration within the first high ion density plasma is reduced using a diffuser to form a second low ion density plasma. The second low ion density plasma is an electron cloud or a dark plasma. An electric field is formed between a substrate support and the diffuser and through the second low ion density plasma during post-exposure bake of a substrate disposed on the substrate support. The second low ion density plasma electrically couples the substrate support and the diffuser during application of the electric field. The plate stack is equipped with power supplies and insulators to enable the formation or modification of a plasma within three regions of a process chamber.

Abstract: A post lithography resist treatment apparatus for treating a substrate having a resist layer thereon with a fluid layer thereover includes at least one post exposure bake chamber comprising a substrate support having a substrate support surface thereon, and an electrode, the electrode comprising an electrode body having a substrate support facing side, the substrate support facing side having at least one recess extending inwardly thereof, and at least one projection adjacent to the recess having a substrate support facing surface thereon, wherein the substrate support is moveable to position a substrate, when supported thereon, such that an fluid layer disposed on the substrate contacts the substrate support facing surface of the projection but does not fill the recess with fluid, and the substrate facing surface of the electrode body is spaced from the substrate.

Abstract: A method for enhancing the depth of focus process window during a lithography process includes applying a photoresist layer comprising a photoacid generator on a material layer disposed on a substrate, exposing a first portion of the photoresist layer unprotected by a photomask to light radiation in a lithographic exposure process, providing a thermal energy to the photoresist layer in a post-exposure baking process, applying an electric field or a magnetic field while performing the post-exposure baking process, and dynamically changing a frequency of the electric field as generated while providing the thermal energy to the photoresist layer.

Abstract: A method of forming graphene layers is disclosed. A method of improving graphene deposition is also disclosed. Some methods are advantageously performed at lower temperatures. Some methods advantageously provide graphene layers with lower resistance. Some methods advantageously provide graphene layers in a relatively short period of time.

Abstract: Embodiments of substrate transfer apparatus are provided herein. In some embodiments, an apparatus for storing and transporting at least one substrate in a vacuum includes a carrying case for storing one or more substrates, wherein the carrying case includes a vacuum port and a plurality of holders to hold one or more substrates within an inner volume of the carrying case; and a vacuum source in fluid connection with the carrying case via the vacuum port.

Abstract: A method of forming graphene layers is disclosed. A method of improving graphene deposition is also disclosed. Some methods are advantageously performed at lower temperatures. Some methods advantageously provide graphene layers with lower resistance. Some methods advantageously provide graphene layers in a relatively short period of time.

Abstract: A film structure for an electric field assisted bake process and methods of forming and implementing such a film structure are described herein. An example is a method for semiconductor processing. A photoresist is deposited on an underlayer disposed on a substrate. The underlayer includes carbon. The photoresist is exposed to a pattern of electromagnetic radiation. After exposing the photoresist, an electric field assisted bake is performed on the photoresist.

Abstract: The present disclosure provides methods for forming a channel structure in a film stack for manufacturing three dimensional (3D) stacked memory cell semiconductor devices. In one embodiment, a memory cell device includes a film stack comprising alternating pairs of dielectric layers and conductive structures horizontally formed on a substrate, and a channel structure formed in the film stack, wherein the channel structure is filled with a channel layer and a protective blocking layer, wherein the channel layer has a gradient dopant concentration along a vertical stacking of the film stack.