Patents by Inventor Ellis Chang
Ellis Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150178914Abstract: Methods and systems for inspection of wafers and reticles using designer intent data are provided. One computer-implemented method includes identifying nuisance defects on a wafer based on inspection data produced by inspection of a reticle, which is used to form a pattern on the wafer prior to inspection of the wafer. Another computer-implemented method includes detecting defects on a wafer by analyzing data generated by inspection of the wafer in combination with data representative of a reticle, which includes designations identifying different types of portions of the reticle. An additional computer-implemented method includes determining a property of a manufacturing process used to process a wafer based on defects that alter a characteristic of a device formed on the wafer. Further computer-implemented methods include altering or simulating one or more characteristics of a design of an integrated circuit based on data generated by inspection of a wafer.Type: ApplicationFiled: March 4, 2015Publication date: June 25, 2015Inventors: Paul Frank Marella, Sharon McCauley, Ellis Chang, William Volk, James Wiley, Sterling Watson, Sagar A. Kekare, Carl Hess
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Publication number: 20150154746Abstract: Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for binning defects detected on a wafer includes comparing portions of design data proximate positions of the defects in design data space. The method also includes determining if the design data in the portions is at least similar based on results of the comparing step. In addition, the method includes binning the defects in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least similar. The method further includes storing results of the binning step in a storage medium.Type: ApplicationFiled: December 19, 2014Publication date: June 4, 2015Inventors: Khurram Zafar, Sagar Kekare, Ellis Chang, Allen Park, Peter Rose
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Publication number: 20150124247Abstract: Methods and systems for determining one or more parameters of a wafer inspection process are provided. One method includes acquiring metrology data for a wafer generated by a wafer metrology system. The method also includes determining one or more parameters of a wafer inspection process for the wafer or another wafer based on the metrology data.Type: ApplicationFiled: October 17, 2014Publication date: May 7, 2015Inventors: Allen Park, Craig MacNaughton, Ellis Chang
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Publication number: 20150120220Abstract: Methods and systems for detecting reliability defects on a wafer are provided. One method includes acquiring output for a wafer generated by an inspection system. The method also includes determining one or more geometric characteristics of one or more patterned features formed on the wafer based on the output. In addition, the method includes identifying which of the one or more patterned features will cause one or more reliability defects in a device being formed on the wafer based on the determined one or more characteristics.Type: ApplicationFiled: October 12, 2014Publication date: April 30, 2015Inventors: Joanne Wu, Ellis Chang, Lisheng Gao, Satya Kurada, Allen Park, Raghav Babulnath
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Patent number: 9002497Abstract: Methods and systems for inspection of wafers and reticles using designer intent data are provided. One computer-implemented method includes identifying nuisance defects on a wafer based on inspection data produced by inspection of a reticle, which is used to form a pattern on the wafer prior to inspection of the wafer. Another computer-implemented method includes detecting defects on a wafer by analyzing data generated by inspection of the wafer in combination with data representative of a reticle, which includes designations identifying different types of portions of the reticle. An additional computer-implemented method includes determining a property of a manufacturing process used to process a wafer based on defects that alter a characteristic of a device formed on the wafer. Further computer-implemented methods include altering or simulating one or more characteristics of a design of an integrated circuit based on data generated by inspection of a wafer.Type: GrantFiled: July 1, 2004Date of Patent: April 7, 2015Assignee: KLA-Tencor Technologies Corp.Inventors: William Volk, James Wiley, Sterling Watson, Sagar A. Kekare, Carl Hess, Paul Frank Marella, Sharon McCauley, Ellis Chang
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Patent number: 8989479Abstract: The present invention includes searching imagery data in order to identify one or more patterned regions on a semiconductor wafer, generating one or more virtual Fourier filter (VFF) working areas, acquiring an initial set of imagery data from the VFF working areas, defining VFF training blocks within the identified patterned regions of the VFF working areas utilizing the initial set of imagery data, wherein each VFF training block is defined to encompass a portion of the identified patterned region displaying a selected repeating pattern, calculating an initial spectrum for each VFF training block utilizing the initial set of imagery data from the VFF training blocks, and generating a VFF for each training block by identifying frequencies of the initial spectrum having maxima in the frequency domain, wherein the VFF is configured to null the magnitude of the initial spectrum at the frequencies identified to display spectral maxima.Type: GrantFiled: August 1, 2011Date of Patent: March 24, 2015Assignee: KLA-Tencor CorporationInventors: Lisheng Gao, Kenong Wu, Allen Park, Ellis Chang, Khurram Zafar, Junqing Huang, Ping Gu, Christopher Maher, Grace H. Chen, Songnian Rong, Liu-Ming Wu
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Inspecting a wafer and/or predicting one or more characteristics of a device being formed on a wafer
Patent number: 8948495Abstract: Methods for inspecting a wafer and/or predicting one or more characteristics of a device being formed on a wafer are provided. One method includes acquiring images for multiple die printed on a wafer, each of which is printed by performing a double patterning lithography process on the wafer and which include two or more die printed at nominal values of overlay for the double patterning lithography process and one or more die printed at modulated values of the overlay; comparing the images acquired for the multiple die printed at the nominal values to the images acquired for the multiple die printed at the modulated values; and detecting defects in the multiple die printed at the modulated values based on results of the comparing step.Type: GrantFiled: March 2, 2013Date of Patent: February 3, 2015Assignee: KLA-Tencor Corp.Inventors: Gino Marcuccilli, Amir Widmann, Ellis Chang, John Robinson, Allen Park -
Patent number: 8923600Abstract: Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for binning defects detected on a wafer includes comparing portions of design data proximate positions of the defects in design data space. The method also includes determining if the design data in the portions is at least similar based on results of the comparing step. In addition, the method includes binning the defects in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least similar. The method further includes storing results of the binning step in a storage medium.Type: GrantFiled: August 3, 2009Date of Patent: December 30, 2014Assignee: KLA-Tencor Technologies Corp.Inventors: Khurram Zafar, Sagar Kekare, Ellis Chang, Allen Park, Peter Rose
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Patent number: 8826200Abstract: Methods and systems for binning defects on a wafer are provided. One method includes identifying areas in a design for a layer of a device being fabricated on a wafer that are not critical to yield of fabrication of the device and generating an altered design for the layer by eliminating features in the identified areas from the design for the layer. The method also includes binning defects detected on the layer into groups using the altered design such that features in the altered design proximate positions of the defects in each of the groups are at least similar.Type: GrantFiled: May 13, 2013Date of Patent: September 2, 2014Assignee: KLA-Tencor Corp.Inventors: Allen Park, Ellis Chang
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Publication number: 20140199791Abstract: Universal target based inspection drive metrology includes designing a plurality of universal metrology targets measurable with an inspection tool and measurable with a metrology tool, identifying a plurality of inspectable features within at least one die of a wafer using design data, disposing the plurality of universal targets within the at least one die of the wafer, each universal target being disposed at least proximate to one of the identified inspectable features, inspecting a region containing one or more of the universal targets with an inspection tool, identifying one or more anomalistic universal targets in the inspected region with an inspection tool and, responsive to the identification of one or more anomalistic universal targets in the inspected region, performing one or more metrology processes on the one or more anomalistic universal metrology targets with the metrology tool.Type: ApplicationFiled: November 18, 2013Publication date: July 17, 2014Applicant: KLA-Tencor CorporationInventors: Allen Park, Ellis Chang, Michael Adel, Kris Bhaskar, Ady Levy, Amir Widmann, Mark Wagner, Songnian Rong
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Publication number: 20140153814Abstract: Mixed-mode includes receiving inspection results including one or more images of a selected region of the wafer, the one or more images include one or more wafer die including a set of repeating blocks, the set of repeating blocks a set of repeating cells. In addition, mixed-mode inspection includes adjusting a pixel size of the one or more images to map each cell, block and die to an integer number of pixels. Further, mixed-mode inspection includes comparing a first wafer die to a second wafer die to identify an occurrence of one or more defects in the first or second wafer die, comparing a first block to a second block to identify an occurrence of one or more defects in the first or second blocks and comparing a first cell to a second cell to identify an occurrence of one or more defects in the first or second cells.Type: ApplicationFiled: November 11, 2013Publication date: June 5, 2014Applicant: KLA-Tencor CorporationInventors: Jason Z. Lin, Allen Park, Ellis Chang, Richard Wallingford, Songnian Rong, Chetana Bhaskar
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Publication number: 20130318485Abstract: Methods and systems for binning defects on a wafer are provided. One method includes identifying areas in a design for a layer of a device being fabricated on a wafer that are not critical to yield of fabrication of the device and generating an altered design for the layer by eliminating features in the identified areas from the design for the layer. The method also includes binning defects detected on the layer into groups using the altered design such that features in the altered design proximate positions of the defects in each of the groups are at least similar.Type: ApplicationFiled: May 13, 2013Publication date: November 28, 2013Applicant: KLA-Tencor CorporationInventors: Allen Park, Ellis Chang
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Patent number: 8594823Abstract: A system and method of matching multiple scanners using design and defect data are described. A golden wafer is processed using a golden tool. A second wafer is processed using a second tool. Both tools provide focus/exposure modulation. Wafer-level spatial signatures of critical structures for both wafers can be compared to evaluate the behavior of the scanners. Critical structures can be identified by binning defects on the golden wafer having similar patterns. In one embodiment, the signatures must match within a certain percentage or the second tool is characterized as a “no match”. Reticles can be compared in a similar manner, wherein the golden and second wafers are processed using a golden reticle and a second reticle, respectively.Type: GrantFiled: July 12, 2010Date of Patent: November 26, 2013Assignee: KLA—Tencor CorporationInventors: Allen Park, Ellis Chang, Masami Aoki, Chris Chih-Chien Young, Martin Plihal, Michael John Van Riet
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Patent number: 8559001Abstract: Inspection guided overlay metrology may include performing a pattern search in order to identify a predetermined pattern on a semiconductor wafer, generating a care area for all instances of the predetermined pattern on the semiconductor wafer, identifying defects within generated care areas by performing an inspection scan of each of the generated care areas, wherein the inspection scan includes a low-threshold or a high sensitivity inspection scan, identifying overlay sites of the predetermined pattern of the semiconductor wafer having a measured overlay error larger than a selected overlay specification utilizing a defect inspection technique, comparing location data of the identified defects of a generated care area to location data of the identified overlay sites within the generated care area in order to identify one or more locations wherein the defects are proximate to the identified overlay sites, and generating a metrology sampling plan based on the identified locations.Type: GrantFiled: January 5, 2011Date of Patent: October 15, 2013Assignee: KLA-Tencor CorporationInventors: Ellis Chang, Amir Widmann, Allen Park
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Publication number: 20130064442Abstract: Methods and systems for determining design coordinates for defects detected on a wafer are provided. One method includes aligning a design for a wafer to defect review tool images for defects detected in multiple swaths on the wafer by an inspection tool, determining a position of each of the defects in design coordinates based on results of the aligning, separately determining a defect position offset for each of the multiple swaths based on the swath in which each of the defects was detected (swath correction factor), the design coordinates for each of the defects, and a position for each of the defects determined by the inspection tool, and determining design coordinates for the other defects detected in the multiple swaths by the inspection tool by applying the appropriate swath correction factor to those defects.Type: ApplicationFiled: August 31, 2012Publication date: March 14, 2013Applicant: KLA-TENCOR CORPORATIONInventors: Ellis Chang, Michael J. Van Riet, Allen Park, Khurram Zafar, Santosh Bhattacharyya
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Publication number: 20120316855Abstract: Various embodiments for using three-dimensional representations for defect-related applications are provided.Type: ApplicationFiled: June 8, 2011Publication date: December 13, 2012Applicant: KLA-TENCOR CORPORATIONInventors: Allen Park, Ellis Chang, Prashant A. Aji, Steven R. Lange
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Publication number: 20120141013Abstract: The present invention includes searching imagery data in order to identify one or more patterned regions on a semiconductor wafer, generating one or more virtual Fourier filter (VFF) working areas, acquiring an initial set of imagery data from the VFF working areas, defining VFF training blocks within the identified patterned regions of the VFF working areas utilizing the initial set of imagery data, wherein each VFF training block is defined to encompass a portion of the identified patterned region displaying a selected repeating pattern, calculating an initial spectrum for each VFF training block utilizing the initial set of imagery data from the VFF training blocks, and generating a VFF for each training block by identifying frequencies of the initial spectrum having maxima in the frequency domain, wherein the VFF is configured to null the magnitude of the initial spectrum at the frequencies identified to display spectral maxima.Type: ApplicationFiled: August 1, 2011Publication date: June 7, 2012Applicant: KLA-TENCOR CORPORATIONInventors: Lisheng Gao, Kenong Wu, Allen Park, Ellis Chang, Khurram Zafar, Junqing Huang, Ping Gu, Christopher Maher, Grace H. Chen, Songnian Rong, Liu-Ming Wu
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Patent number: 8194968Abstract: Various methods and systems for using electrical information for a device being fabricated on a wafer to perform one or more defect-related functions are provided. One computer-implemented method includes using electrical information for a device being fabricated on a wafer to perform one or more defect-related functions. The one or more defect-related functions include one or more post-mask, defect-related functions.Type: GrantFiled: January 7, 2008Date of Patent: June 5, 2012Assignee: KLA-Tencor Corp.Inventors: Allen Park, Peter Rose, Ellis Chang, Brian Duffy, Mark McCord, Gordon Abbott
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Patent number: 8139844Abstract: Various methods and systems for determining a defect criticality index (DCI) for defects on wafers are provided. One computer-implemented method includes determining critical area information for a portion of a design for a wafer surrounding a defect detected on the wafer by an inspection system based on a location of the defect reported by the inspection system and a size of the defect reported by the inspection system. The method also includes determining a DCI for the defect based on the critical area information, a location of the defect with respect to the critical area information, and the reported size of the defect.Type: GrantFiled: April 14, 2008Date of Patent: March 20, 2012Assignee: KLA-Tencor Corp.Inventors: Chien-Huei (Adam) Chen, Yan Xiong, Jianxin Zhang, Ellis Chang, Tsung-Pao Fang
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Publication number: 20110187848Abstract: Computer-implemented methods, computer-readable media, and systems for classifying defects detected in a memory device area on a wafer are provided.Type: ApplicationFiled: July 28, 2009Publication date: August 4, 2011Applicant: KLA-TENCOR CORPORATIONInventors: SunYong Choi, YeonHo Pae, Ellis Chang