Abstract: A system and method of matching multiple scanners using design and defect data are described. A golden wafer is processed using a golden tool. A second wafer is processed using a second tool. Both tools provide focus/exposure modulation. Wafer-level spatial signatures of critical structures for both wafers can be compared to evaluate the behavior of the scanners. Critical structures can be identified by binning defects on the golden wafer having similar patterns. In one embodiment, the signatures must match within a certain percentage or the second tool is characterized as a “no match”. Reticles can be compared in a similar manner, wherein the golden and second wafers are processed using a golden reticle and a second reticle, respectively.

Abstract: Inspection guided overlay metrology may include performing a pattern search in order to identify a predetermined pattern on a semiconductor wafer, generating a care area for all instances of the predetermined pattern on the semiconductor wafer, identifying defects within generated care areas by performing an inspection scan of each of the generated care areas, wherein the inspection scan includes a low-threshold or a high sensitivity inspection scan, identifying overlay sites of the predetermined pattern of the semiconductor wafer having a measured overlay error larger than a selected overlay specification utilizing a defect inspection technique, comparing location data of the identified defects of a generated care area to location data of the identified overlay sites within the generated care area in order to identify one or more locations wherein the defects are proximate to the identified overlay sites, and generating a metrology sampling plan based on the identified locations.

Abstract: Various methods, designs, defect review tools, and systems for determining locations on a wafer to be reviewed during defect review are provided. One computer-implemented method includes acquiring coordinates of defects detected by two or more inspection systems. The defects do not include defects detected on the wafer. The method also includes determining coordinates of the locations on the wafer to be reviewed during the defect review by translating the coordinates of the defects into the coordinates on the wafer such that results of the defect review performed at the locations can be used to determine if the defects cause systematic defects on the wafer.

Abstract: Various computer-implemented methods, carrier media, and systems for generating a metrology sampling plan are provided. One computer-implemented method for generating a metrology sampling plan includes identifying one or more individual defects that have one or more attributes that are abnormal from one or more attributes of a population of defects in which the individual defects are included. The population of defects is located in a predetermined pattern on a wafer. The method also includes generating the metrology sampling plan based on results of the identifying step such that one or more areas on the wafer in which the one or more identified individual defects are located are sampled during metrology.

Abstract: Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for binning defects detected on a wafer includes comparing portions of design data proximate positions of the defects in design data space. The method also includes determining if the design data in the portions is at least similar based on results of the comparing step. In addition, the method includes binning the defects in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least similar. The method further includes storing results of the binning step in a storage medium.

Abstract: Various methods and systems for determining a defect criticality index (DCI) for defects on wafers are provided. One computer-implemented method includes determining critical area information for a portion of a design for a wafer surrounding a defect detected on the wafer by an inspection system based on a location of the defect reported by the inspection system and a size of the defect reported by the inspection system. The method also includes determining a DCI for the defect based on the critical area information, a location of the defect with respect to the critical area information, and the reported size of the defect.

Abstract: The invention is a method for generating a design rule map having a spatially varying overlay error budget. Additionally, the spatially varying overlay error budget can be employed to determine if wafers are fabricated in compliance with specifications. In one approach a design data file that contains fabrication process information and reticle information is processed using design rules to obtain a design map with a spatially varying overlay error budget that defines a localized tolerance to overlay errors for different spatial locations on the design map. This spatially varying overlay error budget can be used to disposition wafers. For example, overlay information obtained from measured metrology targets on a fabricated wafer are compared with the spatially varying overlay error budget to determine if the wafer overlay satisfies the required specification.

Abstract: Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for binning defects detected on a wafer includes comparing portions of design data proximate positions of the defects in design data space. The method also includes determining if the design data in the portions is at least similar based on results of the comparing step. In addition, the method includes binning the defects in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least similar. The method further includes storing results of the binning step in a storage medium.

Abstract: Various computer-implemented methods, carrier media, and systems for generating a metrology sampling plan are provided. One computer-implemented method for generating a metrology sampling plan includes identifying one or more individual defects that have one or more attributes that are abnormal from one or more attributes of a population of defects in which the individual defects are included. The population of defects is located in a predetermined pattern on a wafer. The method also includes generating the metrology sampling plan based on results of the identifying step such that one or more areas on the wafer in which the one or more identified individual defects are located are sampled during metrology.

Abstract: Various methods and systems for using electrical information for a device being fabricated on a wafer to perform one or more defect-related functions are provided. One computer-implemented method includes using electrical information for a device being fabricated on a wafer to perform one or more defect-related functions. The one or more defect-related functions include one or more post-mask, defect-related functions.

Abstract: Various methods, designs, defect review tools, and systems for determining locations on a wafer to be reviewed during defect review are provided. One computer-implemented method includes acquiring coordinates of defects detected by two or more inspection systems. The defects do not include defects detected on the wafer. The method also includes determining coordinates of the locations on the wafer to be reviewed during the defect review by translating the coordinates of the defects into the coordinates on the wafer such that results of the defect review performed at the locations can be used to determine if the defects cause systematic defects on the wafer.

Abstract: Methods and systems for inspection of wafers and reticles using designer intent data are provided. One computer-implemented method includes identifying nuisance defects on a wafer based on inspection data produced by inspection of a reticle, which is used to form a pattern on the wafer prior to inspection of the wafer. Another computer-implemented method includes detecting defects on a wafer by analyzing data generated by inspection of the wafer in combination with data representative of a reticle, which includes designations identifying different types of portions of the reticle. An additional computer-implemented method includes determining a property of a manufacturing process used to process a wafer based on defects that alter a characteristic of a device formed on the wafer. Further computer-implemented methods include altering or simulating one or more characteristics of a design of an integrated circuit based on data generated by inspection of a wafer.

Abstract: The invention is a method for generating a design rule map having a spatially varying overlay error budget. Additionally, the spatially varying overlay error budget can be employed to determine if wafers are fabricated in compliance with specifications. In one approach a design data file that contains fabrication process information and reticle information is processed using design rules to obtain a design map with a spatially varying overlay error budget that defines a localized tolerance to overlay errors for different spatial locations on the design map. This spatially varying overlay error budget can be used to disposition wafers. For example, overlay information obtained from measured metrology targets on a fabricated wafer are compared with the spatially varying overlay error budget to determine if the wafer overlay satisfies the required specification.

Abstract: Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for binning defects detected on a wafer includes comparing portions of design data proximate positions of the defects in design data space. The method also includes determining if the design data in the portions is at least similar based on results of the comparing step. In addition, the method includes binning the defects in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least similar. The method further includes storing results of the binning step in a storage medium.

Abstract: Methods and systems for inspection of wafers and reticles using designer intent data are provided. One computer-implemented method includes identifying nuisance defects on a wafer based on inspection data produced by inspection of a reticle, which is used to form a pattern on the wafer prior to inspection of the wafer. Another computer-implemented method includes detecting defects on a wafer by analyzing data generated by inspection of the wafer in combination with data representative of a reticle, which includes designations identifying different types of portions of the reticle. An additional computer-implemented method includes determining a property of a manufacturing process used to process a wafer based on defects that alter a characteristic of a device formed on the wafer. Further computer-implemented methods include altering or simulating one or more characteristics of a design of an integrated circuit based on data generated by inspection of a wafer.