Abstract: According to embodiments, a system includes a master device and a first memory module having a plurality of integrated circuit memory devices and a plurality of integrated circuit buffer devices that operate in first and second modes of operation (bypass mode). In a first mode of operation, a first memory module provides read data from the plurality of integrated circuit memory devices (via a integrated circuit buffer device) on a first signal path to the master and a second memory module simultaneously provides read data from its plurality of integrated circuit memory devices (via another integrated circuit buffer device on the second module) on a third signal path coupled to the master device.

Abstract: An integrated circuit buffer device comprises a first receiver circuit to receive control information and address information from a controller device. A first interface includes a first interface portion to provide a first address to a first memory device. A second interface portion provides a first control signal to the first memory device. The first control signal specifies a read operation such that the first memory device provides a first data, accessed from a memory location based on the first address, to the integrated circuit buffer device in response to the first control signal specifying the read operation. A third interface portion provides a first clock signal to the first memory device. The first clock signal synchronizes communication of the first control signal from the integrated circuit buffer device to the first memory device. A fourth interface portion receives the first data. A second interface includes a first interface portion to provide a second address to a second memory device.

Abstract: A memory module includes an integrated circuit buffer device that receives control information via a connector interface. A first plurality of signal lines carries a first address from the integrated circuit buffer device to a first memory device. A second plurality of signal lines carries a first control signal from the integrated circuit buffer device to the first memory device. The first control signal specifies a read operation by the first memory device such that the first memory device provides first data, accessed from a memory location in the first memory device based on the first address, to the integrated circuit buffer device. A first signal line carries a first signal from the integrated circuit buffer device to the first memory device. The first signal synchronizes communication of the first control signal from the integrated circuit buffer device to the first memory device. A third plurality of signal lines carries a second address from the integrated circuit device to the second memory device.

Abstract: A method and apparatus for adjusting the performance of a memory system is provided. A memory system comprises a master device and a slave device. A memory channel couples the master device to the slave device such that the slave device receives the system operating information from the master device via the memory channel. The slave device further includes means for tuning circuitry within the slave device such that the performance of the memory system is improved.

Abstract: An integrated circuit buffer device comprising a receiver circuit to receive control information and address information. A first interface portion provides at least a first control signal that specifies a write operation to a first memory device. The first control signal corresponds to the control information. A second interface portion provides a first address to the first memory device. The first address corresponds to the address information. The first address specifies a memory location for the write operation to the first memory device. A third interface portion provides a first signal to the first memory device. The first signal synchronizes communication of the first control signal from the integrated circuit buffer device to the first memory device. A fourth interface portion provides at least a second control signal that specifies a write operation to a second memory device. The second control signal corresponds to the control information.

Abstract: A memory module includes a plurality of signal paths that provide data to a memory module connector interface from a plurality of respective integrated circuit buffer devices that access data from an associated plurality of integrated circuit memory devices. The memory module forms a plurality of “data slices” or a plurality of portions of the memory module data bus that is coupled to the respective integrated circuit buffer devices. Each integrated circuit buffer device is also coupled to a bus that provides control information that specifies an access to at least one integrated circuit memory devices. According to an embodiment, a SPD device stores information regarding configuration information of the memory module. In embodiments, at least one integrated circuit buffer devices access information stored in the SPD device. In a package embodiment, a package houses an integrated circuit buffer die and a plurality of integrated circuit memory dies.

Abstract: A method of testing a dynamic random access memory (DRAM) device that has N rows of storage cells and that requires, in at least one operating mode, at least N refresh commands to be received from an external source within a specified time interval. The rows of storage cells are tested in a first retention test to identify rows that fail to retain data over the specified time interval. The rows that fail to retain data over the specified time interval are tested in a second retention test to identify rows that retain data over an abbreviated time interval, the abbreviated time interval being shorter than the specified time interval.

Abstract: In a dynamic random access memory device, refreshing each normal-retention row of storage cells once per refresh interval, refreshing each low-retention row of storage cells more than once per refresh interval and refreshing each high-retention row of storage cells that is associated with a low-retention row of storage cells once every nth refresh interval.

Abstract: In a dynamic random access memory device, receiving refresh commands via a signaling interface and, in response to the refresh commands, refreshing a first row of storage cells at a first refresh rate and refreshing a second row of storage cells at a second, faster refresh rate.

Abstract: In a memory device having a memory core and a signal interface, receiving a command that specifies at least a portion of a memory access. During the memory access, transferring data between the memory core and the signaling interface, and transferring the data between the signaling interface and an external signal path, and prior to transferring the data between the signaling interface and the external signal path, receiving enable information to selectively enable at least a first memory resource and a second memory resource, wherein each of the first memory resource and the second memory resource performs a control function associated with the memory access.

Abstract: Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.

Abstract: A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.

Abstract: Described are systems that employ configurable on-die termination elements that allow users to select from two or more termination topologies. One topology is programmable to support rail-to-rail or half-supply termination. Another topology selectively includes fixed or variable filter elements, thereby allowing the termination characteristics to be tuned for different levels of speed performance and power consumption. Termination voltages and impedances might also be adjusted.

Abstract: A method, system and memory controller that uses adjustable read data delay settings. The memory controller includes control transmit circuitry, data reception circuitry and timing circuitry. The control circuitry transmits a control signal to multiple memory devices via a shared control signal path. The data reception circuitry receives data signals from the memory devices via respective data signal paths. The timing circuitry delays reception of data signals on each of the data signal paths by a respective time interval that is based, at least in part, on a time required for the control signal to propagate on the control signal path from the memory controller to a respective one of the memory devices.

Abstract: A memory system architecture/interconnect topology that includes at least one point-to-point link between a master, and at least one memory subsystem. The memory subsystem includes a buffer device coupled to a plurality of memory devices. The memory system may be upgraded through dedicated point-to-point links and corresponding memory subsystems. The master communicates to the plurality of memory devices in each memory subsystem through the respective buffer device via each point-to-point link.

Abstract: An integrated circuit buffer device including a first port and a second port. The first port to receive data from a first integrated circuit memory device, and the second port to receive data from a second integrated circuit memory device. The integrated circuit buffer device further includes a multiplexer to output a data stream that includes the data received from the first integrated circuit memory device and the data received from the second integrated circuit memory device. In addition, the integrated circuit buffer device includes an interface including transmit circuitry to transmit the data stream to an integrated circuit controller device.

Abstract: A module having first and second memory devices and a termination component. A first signal line is coupled to the first memory device to provide first data thereto, the first data to be stored in a memory array of the first memory device during a write operation. A second signal line is coupled to the second memory device to provide thereto, the second data to be stored in a memory array of the second memory device during the write operation. A control signal path is coupled to the first memory device, the second memory device and the termination component such that a write command propagating on the control signal path propagates past the first memory device and the second memory device before reaching the first termination component, wherein the write command specifies the write operation.

Abstract: A memory system architecture/interconnect topology that includes at least one point-to-point link between a master, and at least one memory subsystem. The memory subsystem includes a buffer device coupled to a plurality of memory devices. The memory system may be upgraded through dedicated point-to-point links and corresponding memory subsystems.

Abstract: A method, system and memory controller that uses adjustable write data delay settings. The memory controller includes control transmit circuitry, data transmit circuitry and timing circuitry. The control circuitry transmits a control signal to multiple memory devices via a shared control signal path. The data transmit circuitry transmits data signals to the memory devices via respective data signal paths. The timing circuitry delays transmission of data signals on each of the data signal paths by a respective time interval that is based, at least in part, on a time required for the control signal to propagate on the control signal path from the memory controller to a respective one of the memory devices.

Abstract: A memory system architecture/interconnect topology that includes at least one point-to-point link between a master, and at least one memory subsystem. The memory subsystem includes a buffer device coupled to a plurality of memory devices. The memory system may be upgraded through dedicated point-to-point links and corresponding memory subsystems. The master communicates to the plurality of memory devices in each memory subsystem through the respective buffer device via each point-to-point link.