Abstract: A circuit for a switched mode power supply having a winding. The circuit comprising: an input configured to receive a winding voltage derived from the winding; a differentiation element configured to differentiate the winding voltage with respect to time in order to determine a derivative signal and compare the derivative signal with a threshold value; a steady state detector configured to set a zero derivative signal when the derivative signal has not exceeded the threshold value for a predetermined period of time, and a logic arrangement configured to identify an end of a demagnetization stroke of the switched mode power supply when the derivative signal crosses a final threshold value after the zero derivative signal has been set.

Abstract: A method of controlling a switched mode converter is disclosed in which the switching frequency varies in proportion to the square of the sine of the phase of the input AC supply. Thus the switching frequency is a maximum, and the respective on period of the switch is a minimum, when the mains voltage is a maximum. Conversely, the switching frequency is reduced, and the respective on time of the switch is increased, when the mains voltage is reduced. Such a switching method provides for a high power factor. Implementation by means of a phase locked loop and a comparator may prevent the need for complex circuitry, and may provide for direct use of a digital controller or digital signal processing through a counter output in the phase locked loop. A controller configured to operate such a method, together with an AC/DC converter embodying such a controller are also disclosed.

Abstract: A circuit for a switched mode power supply having a winding. The circuit comprising: an input configured to receive a winding voltage derived from the winding; a differentiation element configured to differentiate the winding voltage with respect to time in order to determine a derivative signal and compare the derivative signal with a threshold value; a steady state detector configured to set a zero derivative signal when the derivative signal has not exceeded the threshold value for a predetermined period of time, and a logic arrangement configured to identify an end of a demagnetization stroke of the switched mode power supply when the derivative signal crosses a final threshold value after the zero derivative signal has been set.

Abstract: A method of controlling a switched mode converter is disclosed in which the switching frequency varies in proportion to the square of the sine of the phase of the input AC supply. Thus the switching frequency is a maximum, and the respective on period of the switch is a minimum, when the mains voltage is a maximum. Conversely, the switching frequency is reduced, and the respective on time of the switch is increased, when the mains voltage is reduced. Such a switching method provides for a high power factor. Implementation by means of a phase locked loop and a comparator may prevent the need for complex circuitry, and may provide for direct use of a digital controller or digital signal processing through a counter output in the phase locked loop. A controller configured to operate such a method, together with an AC/DC converter embodying such a controller are also disclosed.

Abstract: A signal processing module with a timing comparator such as a time to digital converter is provided. The timing comparator comprises an error cancellation stage to remove a predicted effect of the imparted jitter from the timing comparator output signal. A jitter detector is used to detect the jitter from the comparator output signal, preferably residual jitter after the predicted effect of the jitter has been removed. Synchronous detection, such as correlation with the predicted jitter may be used to detect the jitter. The jitter detector adjusts a calibration factor of the timing comparator dependent on the detected jitter.

Abstract: A clock signal generator comprising an input pin for receiving an oscillating signal and an output pin for providing a clock signal. The clock signal generator also comprises a frequency divider connected between the input pin and the output pin. The frequency divider having a plurality of frequency division factors associated therewith, wherein, in use, the frequency divider is configured to apply one of the plurality of frequency division factors as an in-use frequency division factor to the oscillating signal in order to generate the clock signal. The clock signal generator further comprising a controller configured to periodically replace the in-use frequency division factor with another of the plurality of frequency division factors.

Abstract: A clock signal generator comprising an input pin for receiving an oscillating signal and an output pin for providing a clock signal. The clock signal generator also comprises a frequency divider connected between the input pin and the output pin. The frequency divider having a plurality of frequency division factors associated therewith, wherein, in use, the frequency divider is configured to apply one of the plurality of frequency division factors as an in-use frequency division factor to the oscillating signal in order to generate the clock signal. The clock signal generator further comprising a controller configured to periodically replace the in-use frequency division factor with another of the plurality of frequency division factors.

Abstract: A signal processing module with a timing comparator such as a time to digital converter is provided. The module may be part of a phase locked loop with a fractional frequency divider that acts to produce a divided down signal modulated with jitter in its timing. The timing comparator comprises an error cancellation stage (30, 24.1, 2060) to remove a predicted effect of the imparted jitter from the timing comparator output signal. A jitter detector (80, 1046, 2064) is used to detect the jitter from the comparator output signal, preferably residual jitter after the predicted effect of the jitter has been removed. Synchronous detection, such as correlation with the predicted jitter may be used to detect the jitter. The jitter detector (80, 1046, 2064) adjusts a calibration factor of the timing comparator dependent on the detected jitter.

Abstract: The present invention relates to a converter circuit and a conversion method for converting an input signal of a first value to an output signal of a second value based on a switched operating mode, wherein an output feedback loop (40) and an additional input forward control loop (60) are provided. The additional input forward control loop (60) serves to correctly control a switching parameter not only with respect to the output load but also over a wide input voltage range. This leads to an improved power efficiency and reliability of the converter circuit.

Abstract: A display device backlight comprises at least one LED and a control circuit for controlling the brightness of the LED, wherein the control circuit comprises a drive transistor for driving a current through the LED and a pulse width modulation circuit for controlling the timing of operation of the drive transistor. A compensation circuit provides a first boost current to the gate of the drive transistor during a rising edge of the current profile and provides a second boost current to the gate of the drive transistor during a falling edge of the current profile. This arrangement improves the switching response of the drive transistor by providing boost currents to/from the gate of the drive transistor during the rising and falling edges of the current through the drive transistor (in response to steps in the PWM control signal).

Abstract: The invention relates to an voltage converter for converting a voltage to multiple output voltages, comprising a first switching circuit (SO) connected to an inductive energy storage element (L) for allowing and interrupting a current flow through the inductive energy storage element (L); at least two second switching circuits (S1) for a controllable discharging of the energy stored in the inductive energy storage element (L), each second switching circuit (S1) being connected to the inductive energy storage element (L) in parallel connection to each other at its respective input and each second switching circuit (S 1) comprising a parasitic element; control voltage selection means for selectively supplying a control voltage to the parasitic element of the switching circuits (S1) such that a current flow trough the parasitic element of the respective switching circuit (1) is inhibited when the second switching circuit (S1) is turned off. A negative influence of parasitic elements (e.g.

Abstract: A device for generating an output clock signal intended to time a digital processing circuit, said generating device receiving a first clock signal, characterized in that it comprises an oscillator generating a second clock signal constituting said output clock signal, said oscillator functioning in a forced mode under the control of the rising and falling edges of said first clock signal, said oscillator functioning in a free mode in the absence of rising or falling edges in said first clock signal, the natural frequency of said oscillator being lower than the frequency of said first clock signal.

Abstract: The present invention relates to a converter circuit and a conversion method for converting an input signal of a first value to an output signal of a second value based on a switched operating mode, wherein an output feedback loop (40) and an additional input forward control loop (60) are provided. The additional input forward control loop (60) serves to correctly control a switching parameter not only with respect to the output load but also over a wide input voltage range. This leads to an improved power efficiency and reliability of the converter circuit.

Abstract: The invention relates to an voltage converter for converting a voltage to multiple output voltages, comprising a first switching circuit (SO) connected to an inductive energy storage element (L) for allowing and interrupting a current flow through the inductive energy storage element (L); at least two second switching circuits (S1) for a controllable discharging of the energy stored in the inductive energy storage element (L), each second switching circuit (S1) being connected to the inductive energy storage element (L) in parallel connection to each other at its respective input and each second switching circuit (S1) comprising a parasitic element; control voltage selection means for selectively supplying a control voltage to the parasitic element of the switching circuits (S1) such that a current flow trough the parasitic element of the respective switching circuit (1) is inhibited when the second switching circuit (S1) is turned off. A negative influence of parasitic elements (e.g.

Abstract: The invention relates to a system for generating an output voltage (Vout) from an input voltage (Vup), said system comprising:—regulation means (T1) for regulating said output voltage (Vout) to a target voltage level (Vcons), said regulation means (T1) comprising a control terminal intended to receive a regulation signal (SR) and an output terminal for delivering said output voltage (Vout),—first control means (COMP1) for delivering a first control signal (SC1) from a comparison between said regulation signal (SR) and a first reference signal (Vref1).

Abstract: The invention relates to a control system for a voltage converter, said control system comprising:—a set of switches (T1-T2-T3-T4) intended to be connected via output terminals (N1-N2-N3) to a first type of voltage converter or to a second type of voltage converter,—detection means (DET) to generate a detection signal (DS) indicating the type of converter connected,—a circuit (CIR) intended to generate, from said detection signal (DS), control signals (CS1-CS2-CS3-CS4) to control said switches (T1-T2-T3-T4).

Abstract: The invention relates to a system for generating an output voltage (Vout) from an input voltage (Vup), said system comprising:—regulation means (T1) for regulating said output voltage (Vout) to a target voltage level (Vcons), said regulation means (T1) comprising a control terminal intended to receive a regulation signal (SR) and an output terminal for delivering said output voltage (Vout),—first control means (COMP1) for delivering a first control signal (SC1) from a comparison between said regulation signal (SR) and a first reference signal (Vref1).

Abstract: The invention relates to a control system for a voltage converter, said control system comprising:—a set of switches (T1-T2-T3-T4) intended to be connected via output terminals (N1-N2-N3) to a first type of voltage converter or to a second type of voltage converter,—detection means (DET) to generate a detection signal (DS) indicating the type of converter connected,—a circuit (CIR) intended to generate, from said detection signal (DS), control signals (CS1-CS2-CS3-CS4) to control said switches (T1-T2-T3-T4).

Abstract: The invention relates to a voltage converter for generating an output voltage at an output terminal from an input voltage VDD taken from ground GND, said voltage converter comprising a switched capacitance Cp arranged in a bridge of transistors of the MOS type functioning as switches, each transistor being controlled by a control signal having a level varying in the rhythm of a clock signal clock. The invention is characterized in that the converter comprises at least a control circuit for supplying said control signal applied between the gate and the source of one of the transistors functioning as a switch, said control circuit having the particular function of generating a control signal having an amplitude which is inversely proportional to the input voltage VDD when the transistor which it controls is equivalent to a closed switch.

Abstract: A device 212 for generating an output clock signal 213 intended to time a digital processing circuit 204, said generating device receiving a first clock signal 209, characterized in that it comprises an oscillator generating a second clock signal constituting said output clock signal, said oscillator functioning in a forced mode under the control of the rising and falling edges of said first clock signal, said oscillator functioning in a free mode in the absence of rising or falling edges in said first clock signal, the natural frequency of said oscillator being lower than the frequency of said first clock signal.