Abstract: A device 212 for generating an output clock signal 213 intended to time a digital processing circuit 204, the generating device receiving a first clock signal 209, characterized in that it comprises an oscillator generating a second clock signal constituting the output clock signal, the oscillator functioning in a forced mode under the control of the rising and falling edges of the first clock signal, the oscillator functioning in a free mode in the absence of rising or falling edges in the first clock signal, the natural frequency of the oscillator being lower than the frequency of the first clock signal. Use: clock signal generator.

Abstract: The invention relates to a voltage converter for generating an output voltage at an output terminal from an input voltage VDD taken from ground GND, said voltage converter comprising a switched capacitance Cp arranged in a bridge of transistors of the MOS type functioning as switches, each transistor being controlled by a control signal having a level varying in the rhythm of a clock signal clock. The invention is characterized in that the converter comprises at least a control circuit for supplying said control signal applied between the gate and the source of one of the transistors functioning as a switch, said control circuit having the particular function of generating a control signal having an amplitude which is inversely proportional to the input voltage VDD when the transistor which it controls is equivalent to a closed switch.

Abstract: A device 212 for generating an output clock signal 213 intended to time a digital processing circuit 204, said generating device receiving a first clock signal 209, characterized in that it comprises an oscillator generating a second clock signal constituting said output clock signal, said oscillator functioning in a forced mode under the control of the rising and falling edges of said first clock signal, said oscillator functioning in a free mode in the absence of rising or falling edges in said first clock signal, the natural frequency of said oscillator being lower than the frequency of said first clock signal.

Abstract: The invention relates to a method of energizing a polyphase motor by means of a plurality of coils (E1, E2, E3), each coil intended to be excited by means of a control signal (I1, I2, I3). The method in accordance with the invention comprises the following steps: identifying the control signal having the largest absolute value, and connecting the corresponding coil to a reference-potential terminal (VCC or GND). The invention enables the losses caused by switching operations in the power stages energizing the coils to be reduced, and to increase the efficiency of the power supply device of the motor.

Abstract: The invention relates to a method of energizing a polyphase motor by means of a plurality of coils (E1, E2, E3), each coil intended to be excited by means of a control signal (I1, I2, I3).