Abstract: A multilevel memory system includes a nonvolatile memory (NVM) device with an NVM media having a media write unit that is different in size than a host write unit of a host controller of the system that has the multilevel memory system. The memory device includes a media controller that controls writes to the NVM media. The host controller sends a write transaction to the media controller. The write transaction can include the write data in host write units, while the media controller will commit data in media write units to the NVM media. The media controller can send a transaction message to indicate whether the write data for the write transaction was successfully committed to the NVM media.

Abstract: A device connected by a link to a host system can include a first port to receive a capability configuration message across a link and a message request receiving logic comprising hardware circuitry to identify a capability of the device identified in the capability configuration message, determine that the capability is to be presented or hidden from operation based on a capability hide enable bit in the capability configuration message, and configure a capability linked list to present or hide the capability based on the determination. The device can also include a message response generator logic comprising hardware circuitry to generate a response message indicating that the capability is to be presented or hidden from operation. The device can include a second port to transmit the response message across the link.

Abstract: An apparatus for generating a data signal comprises a processing circuit configured to generate the data signal, the data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of the first type, the first signal edge and the second signal edge being separated by a first time period corresponding to first data to be transmitted, and the second signal edge and the third signal edge being separated by a second time period corresponding to second data to be transmitted. An output interface circuit is configured to output the data signal.

Abstract: An apparatus for generating a data signal comprises a processing circuit configured to generate the data signal, the data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of the first type, the first signal edge and the second signal edge being separated by a first time period corresponding to first data to be transmitted, and the second signal edge and the third signal edge being separated by a second time period corresponding to second data to be transmitted. An output interface circuit is configured to output the data signal.

Abstract: A multi-level memory architecture scheme to dynamically balance a number of parameters such as power, thermals, cost, latency and performance for memory levels that are progressively further away from the processor in the platform based on how applications are using memory levels that are further away from processor cores. In some examples, the decision making for the state of the far memory (FM) is decentralized. For example, a processor power management unit (p-unit), near memory controller (NMC), and/or far memory host controller (FMHC) makes decisions about the power and/or performance state of the FM at their respective levels. These decisions are coordinated to provide the most optimum power and/or performance state of the FM for a given time. The power and/or performance state of the memories adaptively change to changing workloads and other parameters even when the processor(s) is in a particular power state.

Abstract: Systems or methods of the present disclosure may provide a peripheral component interconnect express (PCIe) device that comprises a programmable fabric. The programmable fabric comprises multiple PCIe physical functions. The programmable fabric also includes switch circuitry having one or more embedded endpoints that dynamically hides or exposes one or more of the multiple PCIe physical functions from a bare metal mode host server without using a reset.

Abstract: Methods, apparatus, and systems for securely providing multiple wake-up time options for PCI Express (PCIe) devices. Under one approach, Vendor Define Messages (VDMs) are exchanged between a host application layer in a host and a device application layer in a PCIe endpoint device coupled to the host via a PCIe link to effect changes to the L1.2 Substate exit time of a PCIe device. Under another approach, Vendor-Specific Extended Capability (VSEC) structures are exchanged between a host application layer and a device application layer to effect the changes. The VDMs and VSEC structures may also be used to enable a host to read Tpower_on capability information defining power modes supported by a PCIe device. Additionally, VSEC implementations are provided that implement VSEC components in the PCIe device transaction layer or the PCIe device application layer.

Abstract: A device connected by a link to a host system can include a first port to receive a capability configuration message across a link and a message request receiving logic comprising hardware circuitry to identify a capability of the device identified in the capability configuration message, determine that the capability is to be presented or hidden from operation based on a capability hide enable bit in the capability configuration message, and configure a capability linked list to present or hide the capability based on the determination. The device can also include a message response generator logic comprising hardware circuitry to generate a response message indicating that the capability is to be presented or hidden from operation. The device can include a second port to transmit the response message across the link.

Abstract: A device connected by a link to a host system can include a first port to receive a capability configuration message across a link and a message request receiving logic comprising hardware circuitry to identify a capability of the device identified in the capability configuration message, determine that the capability is to be presented or hidden from operation based on a capability hide enable bit in the capability configuration message, and configure a capability linked list to present or hide the capability based on the determination. The device can also include a message response generator logic comprising hardware circuitry to generate a response message indicating that the capability is to be presented or hidden from operation. The device can include a second port to transmit the response message across the link.

Abstract: A handshake communication mechanism between a host and an end-point device permits multiple Base Address Registers (BAR registers) to be configured to size or resize the mapped address spaces associated with each BAR register. In one embodiment, the handshake communication mechanism includes a single address space reconfiguration request which may be transmitted in a single transaction layer packet, to request the configuration of multiple BAR registers of an end-point device. Other features and advantages may be realized, depending upon the particular application.

Abstract: In one embodiment, a link training controller is to train a link. The link training controller may be configured to: update a first link parameter of a link setting for the link to a first value; write data to the memory; read the data from the memory using the first value of the first link parameter; and in response to a determination that the data read from the memory does not match the data written to the memory, send an in-band link recovery command to the memory via the link to cause the memory to participate in a link recovery protocol with the apparatus. Other embodiments are described and claimed.

Abstract: Systems and devices can include a power management controller to determine a low power mode exit timing from a plurality of low power mode exit timing options, and cause the setting of a low power mode control register based on the determined low power mode exit timing. A message generator can generate a power mode request message. The power mode request message indicating the determined low power mode exiting timing. The power mode request message can be transmitted to a host across a multilane link.

Abstract: Apparatuses, storage media and methods associated with data transfer, are disclosed herein. In some embodiments, an apparatus for computing comprises: a commit generator and a media write generator. The commit generator is arranged to generate commit indicators correspondingly associated with media slices of a storage media to respectively denote to a storage media controller of the storage media whether to proceed with writing the media slices into the storage media. The media write generator is arranged provide data chunks of the media slices to be written into the storage media, and the associated commit indicators to the storage media controller. A size of each data chunk is smaller than a size of each media slice. Other embodiments are also described and claimed.

Abstract: A multilevel memory system includes a nonvolatile memory (NVM) device with an NVM media having a media write unit that is different in size than a host write unit of a host controller of the system that has the multilevel memory system. The memory device includes a media controller that controls writes to the NVM media. The host controller sends a write transaction to the media controller. The write transaction can include the write data in host write units, while the media controller will commit data in media write units to the NVM media. The media controller can send a transaction message to indicate whether the write data for the write transaction was successfully committed to the NVM media.

Abstract: An apparatus for generating a data signal comprises a processing circuit configured to generate the data signal, the data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of the first type, the first signal edge and the second signal edge being separated by a first time period corresponding to first data to be transmitted, and the second signal edge and the third signal edge being separated by a second time period corresponding to second data to be transmitted. An output interface circuit is configured to output the data signal.

Abstract: The present disclosure provides devices and techniques to dynamically change the operating frequency of an interface where components on the interface have non-common clocks. An interface component may be provided with a frequency negotiation component to negotiate a shift in an operating frequency with other component on an interface where the different components have non-common clocks.

Abstract: Apparatus, systems, and methods to manage memory latency operations are described. In one embodiment, an electronic device comprises a processor and a memory control logic to receive data from a remote memory device, store the data in a local cache memory, receive an error correction code indicator associated with the data, and implement a data management policy in response to the error correction code indicator. Other embodiments are also disclosed and claimed.

Abstract: A device connected by a link to a host system can include a first port to receive a capability configuration message across a link and a message request receiving logic comprising hardware circuitry to identify a capability of the device identified in the capability configuration message, determine that the capability is to be presented or hidden from operation based on a capability hide enable bit in the capability configuration message, and configure a capability linked list to present or hide the capability based on the determination. The device can also include a message response generator logic comprising hardware circuitry to generate a response message indicating that the capability is to be presented or hidden from operation. The device can include a second port to transmit the response message across the link.

Abstract: Apparatuses, storage media and methods associated with data transfer, are disclosed herein. In some embodiments, an apparatus for computing comprises: a commit generator and a media write generator. The commit generator is arranged to generate commit indicators correspondingly associated with media slices of a storage media to respectively denote to a storage media controller of the storage media whether to proceed with writing the media slices into the storage media. The media write generator is arranged provide data chunks of the media slices to be written into the storage media, and the associated commit indicators to the storage media controller. A size of each data chunk is smaller than a size of each media slice. Other embodiments are also described and claimed.

Abstract: A hardware platform includes a nonvolatile storage device that can store system firmware as well as code for the primary operating system for the hardware platform. The hardware platform includes a controller that determines the hardware platform lacks functional firmware to boot the primary operating system from the storage device. The controller accesses a firmware image from an external interface that interfaces a device external to the hardware platform, where the external device is a firmware image source. The controller provisions the firmware from the external device to the storage device and initiates a boot sequence from the provisioned firmware.