Abstract: In an embodiment, an apparatus is provided that may include circuitry to, in response at least in part to detected change in at least one of acceleration and orientation of storage, request suspension of at least one command currently stored in at least one pending command queue that is intended for execution, at least in part, by the storage. The at least one command having been previously issued by the circuitry but being currently unexecuted, at least in part, by the storage. The circuitry also being to store, in response at least in part to the detected change, at least one copy of the at least one command for later re-issuance by the circuitry, and to request replacement of at least one command in the at least one queue with at least one other command to park at least one head of the storage.

Abstract: A method, apparatus, system, and computer program product for enabling out-of-band access to storage devices through port-sharing hardware. Providing out-of-band access to storage devices enables system management functions to be performed when an operating system is non-functional as well as when the operating system is active. Storage commands originating with a management service can be interleaved with storage commands issued by the host operating system. The host operating system maintains ownership and control over its storage devices, but management activities can be performed while the host operating system is operational.

Abstract: A host device and a storage device with a Serial ATA (SATA) architecture to independently transition to a deeper low power state after first entering an initial low power state without first transitioning to the Active state. The transition from the Partial state to the Slumber state is direct and the transition may be enabled, but not negotiated through a handshaking process.

Abstract: In one embodiment, the present invention includes a method for transmitting a frame information structure (FIS) message from a host controller or receiving a FIS message at the host controller, transmitting a synchronization signal from the host controller to a port multiplier coupled to the host controller via a link and sustaining a transmit ready signal from the host controller to the port multiplier to thereby lock the link between the host controller and the port multiplier after sending the synchronization signal, and transmitting multiple command FIS messages from the host controller to the port multiplier in a back-to-back manner, where the back-to-back command FIS messages are directed to different devices. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a host controller having a cache memory to store entries each including, at least, a command header (CH) portion having data associated with a command from the host controller to one of multiple devices coupled to a port multiplier, and a physical region descriptor (PRD) portion to store address information associated with a next address for data transfer with regard to the command. Other embodiments are described and claimed.

Abstract: A method, device, and system are disclosed. In one embodiment method begins by receiving a first new mass storage disk access request. The method then determines the total number of access requests to the mass storage disk received in a window of time. If the total number of requests received over the period of time is greater than or equal to a request threshold number then a request frequency counter is decremented. Otherwise, the counter is incremented. The method continues by generating a legacy advanced technology attachment (ATA)-type command for the first new access request when the counter is greater than or equal to a counter threshold number. Otherwise, the method generates a native command queue (NCQ)-type command for the first new access request.

Abstract: In an embodiment, an apparatus is provided that may include circuitry to, in response at least in part to detected change in at least one of acceleration and orientation of storage, request suspension of at least one command currently stored in at least one pending command queue that is intended for execution, at least in part, by the storage. The at least one command having been previously issued by the circuitry but being currently unexecuted, at least in part, by the storage. The circuitry also being to store, in response at least in part to the detected change, at least one copy of the at least one command for later re-issuance by the circuitry, and to request replacement of at least one command in the at least one queue with at least one other command to park at least one head of the storage.

Abstract: A host device and a storage device with a Serial ATA (SATA) architecture to independently transition to a deeper low power state after first entering an initial low power state without first transitioning to the Active state. The transition from the Partial state to the Slumber state is direct and the transition may be enabled, but not negotiated through a handshaking process.

Abstract: An access detector detects an access type of an access to one of a plurality of serial ports interfacing to serial storage devices. The access is intended to one of a plurality of parallel channels interfacing to parallel storage devices via task file registers of the parallel channels. A mapping circuit maps the serial ports to the parallel channels. A state machine emulates a response from the one of the parallel channels based on the access type and the mapped serial ports.

Abstract: A method, circuit, and system are disclosed. In one embodiment, the method comprises sending a step pulse across a serial advanced technology attachment (SATA) transmission line, determining the length of time the transmission line takes to charge from common mode voltage to supply voltage, and determining whether a device is connected to the SATA transmission line based on the length of the transmission line charge time.

Abstract: In one embodiment, the present invention includes a method for transmitting a frame information structure (FIS) message from a host controller or receiving a FIS message at the host controller, transmitting a synchronization signal from the host controller to a port multiplier coupled to the host controller via a link and sustaining a transmit ready signal from the host controller to the port multiplier to thereby lock the link between the host controller and the port multiplier after sending the synchronization signal, and transmitting multiple command FIS messages from the host controller to the port multiplier in a back-to-back manner, where the back-to-back command FIS messages are directed to different devices. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a host controller having a cache memory to store entries each including, at least, a command header (CH) portion having data associated with a command from the host controller to one of multiple devices coupled to a port multiplier, and a physical region descriptor (PRD) portion to store address information associated with a next address for data transfer with regard to the command. Other embodiments are described and claimed.

Abstract: A method, circuit, and system are disclosed. In one embodiment, the method comprises sending a step pulse across a serial advanced technology attachment (SATA) transmission line, determining the length of time the transmission line takes to charge from common mode voltage to supply voltage, and determining whether a device is connected to the SATA transmission line based on the length of the transmission line charge time.

Abstract: An access detector detects an access type of an access to one of a plurality of serial ports interfacing to serial storage devices. The access is intended to one of a plurality of parallel channels interfacing to parallel storage devices via task file registers of the parallel channels. A mapping circuit maps the serial ports to the parallel channels. A state machine emulates a response from the one of the parallel channels based on the access type and the mapped serial ports.

Abstract: An access detector detects an access type of an access to one of a plurality of serial ports interfacing to serial storage devices. The access is intended to one of a plurality of parallel channels interfacing to parallel storage devices via task file registers of the parallel channels. A mapping circuit maps the serial ports to the parallel channels. A state machine emulates a response from the one of the parallel channels based on the access type and the mapped serial ports.